Universal FPGA array loading, updating and maintaining system and method

Abstract

The invention provides a universal FPGA array loading, updating and maintaining system, which comprises an array loading module connected with an FPGA array, the array loading module comprises a memory bank and is used for storing program loading data of the FPGA array; the updating interface is used for being connected with the outside to obtain program updating data from the outside; the data centralized storage management module is used for grouping the FPGA arrays and correspondingly configuring an independent loading channel for each group of FPGAs; the data updating module is used for storing the acquired program updating data in the memory bank so as to update the corresponding program loading data; and the loading module is used for loading the program loading data in the memory bank to the grouped FPGA array through a loading channel according to a preset loading sequence and a loading mode. The method comprises the steps of update obtaining, program storage, grouping configuration and update loading. Unified storage, updating, loading, maintenance and other management operations are carried out on program data of a plurality of FPGAs in the array, and the requirements ofthe FPGA array for the capacity, the number and hardware interfaces of a memory bank are reduced.

Description

technical field [0001] The invention relates to FPGA update management, in particular to a general FPGA array loading update maintenance system and method. Background technique [0002] FPGA arrays are used in the design of electronic equipment in various industries. They have the characteristics of high concurrent processing and customizable logic programs. FPGA arrays are used in many supercomputing nodes, communication nodes, and data processing acceleration nodes. [0003] At this stage, FPGA loading methods are various: parallel flash, serial flash, SelectMap, etc., but the fundamental design solution is that one FPGA is configured with a piece of program memory, and the program loading and updating of the FPGA array is performed by each piece of FPGA for its own program memory. The memory does data read and data change operations. Such a design will lead to redundant program memory of the FPGA, inconvenient maintenance, and high hardware cost and maintenance costs; it...

AI Technical Summary

Problems solved by technology

Such a design will lead to redundant program memory of the FPGA, inconvenient maintenance, and high hardware cost and maintenance cost; it cannot achieve memory reuse, program data reuse, inconvenient batch management, and inconvenient remote update.

[0004] At present, the program update and management of the FPGA array depends on the intervention of the emulator. There are problems such as the difficulty of inserting the emulator and the limited space of the emulator hardware interface. Moreover, the program loading mode and loading behavior of the FPGA have been solidified once the hardware design is completed. Change

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