fpga device with adjustable power-on reset signal waveform

Abstract

The application discloses an FPGA device with a power-on reset signal waveform adjustable function, which relates to the field of FPGA technology. module, the input terminal of the reset signal control module is connected to the output terminal of the power-on reset circuit and obtains the first power-on reset pulse signal output by the power-on reset circuit, and the reset signal control module selects one of several control signals obtained from the control terminal The control signal is used to adjust the waveform of the first power-on reset pulse signal to obtain the second power-on reset pulse signal to output to the power circuit, so as to affect the power-on process of the power circuit in the FPGA die, and reset the control signal of the signal control module There are various sources of power-on reset controllable, including but not limited to sequence controllable, duration controllable and external controllable.

Description

Technical field [0001] The present invention relates to the field of FPGA, in particular, an FPGA device having a power-on reset signal waveform adjustable function. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable logic device, which is widely used in mobile communications, data centers, navigation guidance and automatic driving. FPGAs are often designed to power-on reset, por-on reset, por circuit in the FPGA within the FPGA, and the POWER-ON RESET (POR) circuit is usually designed to power the power-on reset, por circuit, to ensure that the Power-on Reset, POR circuit is designed to power the power-on reset, por. The state is correct during the power-on, but the circuit structure of the existing power-up reset circuit is typically fixed, and the generated power-up reset pulse signal is also fixed, the flexibility is poor. Inventive content [0003] The inventors provide an FPGA apparatus having ...

AI Technical Summary

Problems solved by technology

In the power-on stage of the FPGA, because the power supply signal cannot immediately reach the working voltage, in order to maintain the internal working state of the FPGA, a Power-On Reset (POR) circuit is usually designed inside the FPGA to generate a power-on reset pulse signal to ensure that the FPGA internal The state of the circuit is correct during the power-on process, but the circuit structure of the existing power-on reset circuit is usually fixed, and the generated power-on reset pulse signal is also fixed, and the flexibility is poor

Images