Random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous calculation

A random walk algorithm and random walk technology, applied in computer, computer-aided design, digital computer components, etc., can solve problems such as limited FPGA chip resources and weak circuit control capabilities

Pending Publication Date: 2020-10-20

FUDAN UNIV

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AI-Extracted Technical Summary

Problems solved by technology

[0007] The research shows that the key difficulty in using the SDAccel tool to implement the random walk algorithm on the FPGA lies in the limited resources on the...

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous computing. The method comprises: after a GDS layout is read in a CPU, a Gaussian plane is generated, initial points are generated, the layout is segmented and blocks are screened, operating a random walk algorithmin an FPGA for each block containing the initial points; and completing a path which exceeds a block boundary or does not touch any conductor in the FPGA in the CPU, and calculating a final parasiticcapacitance result. The method is simple and regular in algorithm, does not need a complex space management strategy, still has a relatively high energy efficiency ratio, can be repeatedly used for different GDS layouts after the FPGA bit streams for processing the blocks are generated through one-time compiling, and is high in practicability. The invention particularly provides an FPGA and CPU heterogeneous computing framework suitable for random walk parasitic capacitance parameter extraction. And a layout segmentation method and an optimization method for improving the FPGA code parallel efficiency are provided for the framework.

Application Domain

Computer aided designEnergy efficient computing +2

Technology Topic

Integrated circuitHigh energy +4

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Examples

Experimental program(1)

Example Embodiment

[0142] Through the implementation process of specific examples, the method of the present invention is further described.

[0143] In the random walking capacitance parameter extraction algorithm of the present invention, the FPGA-CPU heterogeneous computing platform uses an AWS (Amazon Web Services) EC2F1 instance, where the CPU is an Intel Xeon E5-2686 8-core processor with a frequency of 2.3 GHz, and the memory is 122 GB , FPGA development board is equipped with Xilinx Virtex UltraScale+VU9P FPGA and 64GB onboard memory. At the same time, FPGA development tool is Xilinx SDAccel tool 2017.1 version, using 32-bit floating point numbers.

[0144] Implementation example 1

[0145] This example uses Picture 10 The circuit shown is similar to the calculation examples used in [11] and [12].

[0146] This calculation example includes three layers of 41 conductors, including 3 conductors in the M2 layer, and 19 conductors in each of M1 and M3. In this calculation example, the conductor space is divided into 4 pieces, and 100 initial points are taken on the Gaussian surface. Total running 1.02×10 5 The number of random walking computing cores running in parallel is 8;

[0147] As shown in Table 1, in this calculation example, the speedup ratio relative to the calculation speed of the Intel Core i5-4570 quad-core CPU is 6.09x, and the speedup ratio for calculating energy efficiency is 42.63x;

[0148] Table 1 Test results of example 1

[0149]

[0150] The random walking algorithm used in the present invention is the standard WOS algorithm, while the optimized WOC algorithm used in [11] and [12] requires complex preprocessing. Table 2 compares the present invention with the standard algorithm CPU implementation, CPU implementation of optimized algorithm [11], GPU implementation of optimized algorithm [12], and GPU implementation of standard algorithm [12], the results show that the present invention still has 5.2x compared to the CPU (8 core) implementation of optimized algorithm Energy efficiency speedup ratio.

[0151] Table 2 Energy efficiency comparison between the present invention and existing CPU and GPU platform algorithms

[0152] .

[0153] Implementation example 2

[0154] In order to use a larger-scale circuit for verification, this example will Picture 10 The circuit shown has been expanded, that is, the number of conductors on the M1 and M3 layers has been expanded from 19 per layer to 800 per layer, and the length of the 3 conductors on the M2 layer has been increased accordingly; in this example, the conductors The space is divided into 20 blocks, 2522 initial points are taken on the Gaussian surface, and a total of 1.01×10 is run 7 There are 8 paths, and the number of random walking algorithm cores running in parallel is 8;

[0155] As shown in Table 3, in this calculation example, the speedup ratio of the present invention relative to the efficiency of the Intel Core i5-4570 quad-core CPU is 4.92x, and the speedup ratio of energy efficiency is 37.58x.

[0156] Table 3 Test results of Example 2

[0157] .

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