Random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous calculation
A random walk algorithm and random walk technology, applied in computer, computer-aided design, digital computer components, etc., can solve problems such as limited FPGA chip resources and weak circuit control capabilities
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[0142] Through the implementation process of specific examples, the method of the present invention is further described.
[0143] In the random walk capacitance parameter extraction algorithm of the present invention, the FPGA-CPU heterogeneous computing platform uses an AWS (Amazon Web Services) EC2F1 instance, wherein the CPU is an Intel Xeon E5-2686 8-core processor with a main frequency of 2.3GHz and a memory of 122GB , The FPGA development board is equipped with Xilinx Virtex UltraScale+VU9P FPGA and 64GB onboard memory. At the same time, the FPGA development tool is Xilinx SDAccel tool version 2017.1, using 32-bit floating point numbers.
[0144] Implementation example 1
[0145] This example uses the Figure 10 The circuit shown is similar to the examples used in [11], [12].
[0146] This calculation example includes three layers of 41 conductors, including 3 conductors in M2 layer, 19 conductors in M1 and M3 respectively. In this calculation example, the conductor s...
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