Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous calculation

A random walk algorithm and random walk technology, applied in computer, computer-aided design, digital computer components, etc., can solve problems such as limited FPGA chip resources and weak circuit control capabilities

Pending Publication Date: 2020-10-20
FUDAN UNIV
View PDF0 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The research shows that the key difficulty in using the SDAccel tool to implement the random walk algorithm on the FPGA lies in the limited resources on the FPGA chip. Secondly, the SDAccel tool uses C-like compiling instructions (pragma) to realize the control of the synthesis and the underlying circuit. weak control

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous calculation
  • Random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous calculation
  • Random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous calculation

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0142] Through the implementation process of specific examples, the method of the present invention is further described.

[0143] In the random walk capacitance parameter extraction algorithm of the present invention, the FPGA-CPU heterogeneous computing platform uses an AWS (Amazon Web Services) EC2F1 instance, wherein the CPU is an Intel Xeon E5-2686 8-core processor with a main frequency of 2.3GHz and a memory of 122GB , The FPGA development board is equipped with Xilinx Virtex UltraScale+VU9P FPGA and 64GB onboard memory. At the same time, the FPGA development tool is Xilinx SDAccel tool version 2017.1, using 32-bit floating point numbers.

[0144] Implementation example 1

[0145] This example uses the Figure 10 The circuit shown is similar to the examples used in [11], [12].

[0146] This calculation example includes three layers of 41 conductors, including 3 conductors in M2 layer, 19 conductors in M1 and M3 respectively. In this calculation example, the conductor s...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous computing. The method comprises: after a GDS layout is read in a CPU, a Gaussian plane is generated, initial points are generated, the layout is segmented and blocks are screened, operating a random walk algorithmin an FPGA for each block containing the initial points; and completing a path which exceeds a block boundary or does not touch any conductor in the FPGA in the CPU, and calculating a final parasiticcapacitance result. The method is simple and regular in algorithm, does not need a complex space management strategy, still has a relatively high energy efficiency ratio, can be repeatedly used for different GDS layouts after the FPGA bit streams for processing the blocks are generated through one-time compiling, and is high in practicability. The invention particularly provides an FPGA and CPU heterogeneous computing framework suitable for random walk parasitic capacitance parameter extraction. And a layout segmentation method and an optimization method for improving the FPGA code parallel efficiency are provided for the framework.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to a random walk parasitic capacitance parameter extraction method, in particular to a random walk based on FPGA (Field Programmable Gate Array, field programmable gate array) and CPU (Central Processing Unit, central processing unit) heterogeneous calculation (Random Walk) parasitic capacitance parameter extraction method. Background technique [0002] With the development of deep submicron VLSI, the metal line width gradually decreases, the chip scale continues to expand, and the total length and layer number of interconnect lines also gradually increase, resulting in the delay caused by the parasitic capacitance of interconnect lines. The proportion of time in the total time delay is increasing [1], how to quickly and accurately calculate the parasitic capacitance parameters of interconnection lines has become an important research topic in domestic and foreign academic and indus...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F30/392G06F15/78
CPCG06F15/7807Y02D10/00
Inventor 曾璇严昌浩周海周电韦昕
Owner FUDAN UNIV
Features
  • Generate Ideas
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More