Random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous calculation

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a random walk parasitic capacitance parameter extraction method based on FPGA and CPU heterogeneous computing. The method comprises: after a GDS layout is read in a CPU, a Gaussian plane is generated, initial points are generated, the layout is segmented and blocks are screened, operating a random walk algorithmin an FPGA for each block containing the initial points; and completing a path which exceeds a block boundary or does not touch any conductor in the FPGA in the CPU, and calculating a final parasiticcapacitance result. The method is simple and regular in algorithm, does not need a complex space management strategy, still has a relatively high energy efficiency ratio, can be repeatedly used for different GDS layouts after the FPGA bit streams for processing the blocks are generated through one-time compiling, and is high in practicability. The invention particularly provides an FPGA and CPU heterogeneous computing framework suitable for random walk parasitic capacitance parameter extraction. And a layout segmentation method and an optimization method for improving the FPGA code parallel efficiency are provided for the framework.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to a random walk parasitic capacitance parameter extraction method, in particular to a random walk based on FPGA (Field Programmable Gate Array, field programmable gate array) and CPU (Central Processing Unit, central processing unit) heterogeneous calculation (Random Walk) parasitic capacitance parameter extraction method. Background technique [0002] With the development of deep submicron VLSI, the metal line width gradually decreases, the chip scale continues to expand, and the total length and layer number of interconnect lines also gradually increase, resulting in the delay caused by the parasitic capacitance of interconnect lines. The proportion of time in the total time delay is increasing [1], how to quickly and accurately calculate the parasitic capacitance parameters of interconnection lines has become an important research topic in domestic and foreign academic and indus...

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Problems solved by technology

[0007] The research shows that the key difficulty in using the SDAccel tool to implement the random walk algorithm on the FPGA lies in the limited resources on the FPGA chip. Secondly, the SDAccel tool uses C-like compiling instructions (pragma) to realize the control of the synthesis and the underlying circuit. weak control

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