Image compression hardware accelerator device based on convolution automatic coding algorithm
A hardware accelerator and image compression technology, applied in image communication, electrical components, digital video signal modification, etc., can solve the problems of computing power constraints, image reconstruction quality cannot be improved to the maximum extent, single compression method, etc.
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[0016] Further description will be made below in conjunction with the accompanying drawings and the specific implementation of the present invention. Where the same name is used throughout to refer to modules with the same or similar functionality. The present device will be specifically described below by referring to the implementation examples described with reference to the accompanying drawings. The implementation example selects an image with a resolution of 4K (3840*2160) and utilizes the periodic parallel convolution acceleration capability of the device to process the compression task, which is intended to explain the present invention, but should not be construed as a limitation of the present invention.
[0017] Such as figure 1 Shown is the top-level hardware architecture diagram of the device of the present invention. The image compression hardware accelerator device based on the convolutional auto-encoding algorithm includes:
[0018] 1. Control unit: responsi...
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