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Image compression hardware accelerator device based on convolution automatic coding algorithm

A hardware accelerator and image compression technology, applied in image communication, electrical components, digital video signal modification, etc., can solve the problems of computing power constraints, image reconstruction quality cannot be improved to the maximum extent, single compression method, etc.

Inactive Publication Date: 2020-10-20
NANJING UNIV
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Problems solved by technology

Traditional lossy image compression has the following disadvantages: 1) The compression ratio is low, which cannot meet the image compression requirements in some harsh scenes and the application purposes of transmission and storage; 2) The compression method is single, usually relying on transformation, quantization and The entropy coding method cannot include the image content as an influencing factor in the compression task, resulting in the inability to maximize the image reconstruction quality after decompression
Due to the influence of computational complexity, the current automatic coding algorithm used in image compression methods, especially the automatic coding algorithm combined with convolutional neural network, faces a series of computing power constraints and resource constraints in promotion and application. challenge
[0004] In view of the advantages and disadvantages of self-encoding algorithm applied to image compression, the author of the present invention designed the accelerator device of the present invention by studying and solving the problem of excessive resource consumption in the hardware implementation of the algorithm

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  • Image compression hardware accelerator device based on convolution automatic coding algorithm
  • Image compression hardware accelerator device based on convolution automatic coding algorithm
  • Image compression hardware accelerator device based on convolution automatic coding algorithm

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Embodiment Construction

[0016] Further description will be made below in conjunction with the accompanying drawings and the specific implementation of the present invention. Where the same name is used throughout to refer to modules with the same or similar functionality. The present device will be specifically described below by referring to the implementation examples described with reference to the accompanying drawings. The implementation example selects an image with a resolution of 4K (3840*2160) and utilizes the periodic parallel convolution acceleration capability of the device to process the compression task, which is intended to explain the present invention, but should not be construed as a limitation of the present invention.

[0017] Such as figure 1 Shown is the top-level hardware architecture diagram of the device of the present invention. The image compression hardware accelerator device based on the convolutional auto-encoding algorithm includes:

[0018] 1. Control unit: responsi...

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Abstract

The invention discloses an image compression hardware accelerator device based on a convolution automatic coding algorithm. The device is mainly composed of a control unit, a logic calculation acceleration unit and a storage unit. The control unit mainly comprises control over the logic calculation acceleration unit and control over the storage unit. The logic calculation acceleration unit comprises a convolution calculation array composed of a multiplexing processor, a periodic parallel convolution calculation unit and a calculation unit; and a storage unit comprises a pixel memory, a weightmemory, a result memory and an off-chip dynamic memory. The acceleration of the device for image compression is mainly as follows: convolution splitting is performed according to image characteristics; the calculation parallelism degree is increased; and periodic convolution control is performed. Due to the working characteristics of periodic convolution splitting and high degree of parallelism ofthe device, the convolution automatic coding algorithm can be very effectively utilized, compression processing acceleration is carried out on the image, excessive hardware resource consumption is avoided, and certain innovativeness is achieved.

Description

technical field [0001] The invention relates to the technical fields of computer and electronic information, in particular to an image compression hardware accelerator device based on a convolutional automatic encoding algorithm. Background technique [0002] Image is the visual basis of human perception of the world, and its compression technology has always been an important issue in digital signal processing. The purpose of image compression is to reduce the amount of data required to represent digital images by compressing images on the premise of ensuring accuracy. The essence of image compression is to achieve higher quality image reconstruction tasks at the pixel level with less coding bit rate. Image compression can be divided into two categories of lossy compression and lossless compression according to the compression method. Lossless image compression technology is widely used in fields requiring high image precision because it can ensure the integrity of the im...

Claims

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Application Information

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IPC IPC(8): H04N19/42
CPCH04N19/42
Inventor 王中风李文斌林军
Owner NANJING UNIV
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