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SOI field effect transistor with electric leakage shielding structure and preparation method thereof

A technology of field effect transistors and shielding structures, which is applied in transistors, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as leakage and failure, and achieve the effect of reducing leakage channels

Active Publication Date: 2020-11-17
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a SOI field effect transistor with a leakage shielding structure and a preparation method thereof, which is used to solve the problem that the SOI field effect transistor has a large total dose effect in the prior art. Amplitude response causes problems such as leakage or even failure

Method used

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  • SOI field effect transistor with electric leakage shielding structure and preparation method thereof
  • SOI field effect transistor with electric leakage shielding structure and preparation method thereof
  • SOI field effect transistor with electric leakage shielding structure and preparation method thereof

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Embodiment 1

[0071] Such as figure 1 As shown, removing the insulating layer (BOX layer) below the channel of the SOI transistor can effectively prevent the total dose effect. This solution removes the insulating layer below the transistor channel to form a groove 101, which can effectively reduce the total dose effect. However, In the structure, the insulating layer (BOX layer) still has overlapping contact portion 102 with the conductive channel. When the total dose effect occurs, it will cause leakage in the direction of the dashed line.

[0072] Based on the above problems, such as Figure 2 to Figure 39 As shown, the present embodiment provides a method for preparing an SOI field effect transistor with a leakage shielding structure, and the method for preparing includes the steps of:

[0073] Such as Figure 2 to Figure 4 As shown, step 1) is first performed to provide a patterned SOI substrate 200, the patterned SOI substrate 200 includes a bottom substrate 201, an insulating laye...

Embodiment 2

[0101] This embodiment provides an SOI field effect transistor with a leakage shielding structure, the SOI field effect transistor with a leakage shielding structure can be prepared by the preparation method of the first embodiment above, but is not limited to the preparation method of the first embodiment, as long as it can be formed An SOI field effect transistor with a leakage shielding structure may be sufficient. For the beneficial effects achieved by the SOI field effect transistor with the leakage shielding structure, please refer to Embodiment 1, which will not be repeated below.

[0102] Such as Figure 2 to Figure 4 , Figure 35 to Figure 39 As shown, the SOI field effect transistor with leakage shielding structure includes:

[0103] A patterned SOI substrate 200, the patterned SOI substrate 200 includes a bottom substrate 201, an insulating layer 202 and a top semiconductor layer 203, the insulating layer 202 below the top semiconductor layer 203 has a The groove...

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Abstract

The invention provides an SOI field effect transistor with an electric leakage shielding structure and a preparation method, and the structure comprises a graphical SOI substrate which is provided with a bottom substrate, an insulating layer and a top semiconductor layer in the shape of a semiconductor island, the insulating layer is provided with a groove, and the semiconductor island completelycovers the groove; the first conduction type heavily doped regions are formed at two ends of the top semiconductor layer extending in the second direction above the groove, and the width of the firstconduction type heavily doped regions in the second direction is greater than the width of an overlapping region of the top semiconductor layer extending in the second direction above the groove and the insulating layer; the gate structure is formed above the groove; the source region and the drain region of the second conductive type are formed at the two ends of the gate structure; and the bodybias electrode is formed on the first conductive type heavily doped region. By arranging the heavily doped region of the first conductive type and the body bias electrode, the height of a PN junctionbarrier formed by the channel inversion layer and the heavily doped region is effectively adjusted, an electric leakage channel caused by the total dose effect is effectively eliminated, and the device is enabled to have zero response to the total dose effect.

Description

technical field [0001] The invention belongs to the field of semiconductor design and manufacture, in particular to an SOI field effect transistor with a leakage shielding structure and a preparation method thereof. Background technique [0002] Field effect transistors on SOI substrates have good anti-single event effects, but because in the SOI structure, the insulating layer (BOX layer) tends to accumulate more induced charges when high-energy particles are incident, the induced charges are on the top layer of SOI silicon The parasitic conductive channel is caused in the middle, which introduces the leakage current and makes the electrical performance of the device drift. This effect is called the total dose effect, and the total dose effect is the main reason for the failure of SOI transistors in the environment of high-energy particle irradiation. Contents of the invention [0003] In view of the shortcomings of the prior art described above, the purpose of the prese...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/06H01L29/423H01L29/786
CPCH01L29/0638H01L29/0684H01L29/4238H01L29/42376H01L29/66742H01L29/78603H01L29/78609
Inventor 刘强俞文杰
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI