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Soi field effect transistor with leakage shielding structure and preparation method thereof

A technology of field effect transistors and shielding structures, which is applied in transistors, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as leakage and failure, and achieve the effect of reducing leakage channels

Active Publication Date: 2022-06-24
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a SOI field effect transistor with a leakage shielding structure and a preparation method thereof, which is used to solve the problem that the SOI field effect transistor has a large total dose effect in the prior art. Amplitude response causes problems such as leakage or even failure

Method used

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  • Soi field effect transistor with leakage shielding structure and preparation method thereof
  • Soi field effect transistor with leakage shielding structure and preparation method thereof
  • Soi field effect transistor with leakage shielding structure and preparation method thereof

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Embodiment 1

[0071] like figure 1 As shown, removing the insulating layer (BOX layer) under the channel of the SOI transistor can effectively prevent the total dose effect. This solution removes the insulating layer under the transistor channel to form the groove 101, which can effectively reduce the total dose effect. However, In the structure, the insulating layer (BOX layer) still has an overlapping contact portion 102 with the conductive channel. When the total dose effect occurs, leakage current in the direction of the dashed line will be caused.

[0072] Based on the above problems, such as Figure 2 to Figure 39 As shown, the present embodiment provides a method for fabricating an SOI field effect transistor with a leakage shielding structure, the fabrication method comprising the steps of:

[0073] like Figure 2 to Figure 4 As shown, step 1) is first performed to provide a patterned SOI substrate 200 , the patterned SOI substrate 200 includes a bottom substrate 201 , an insulat...

Embodiment 2

[0101] This embodiment provides an SOI field effect transistor with a leakage shielding structure. The SOI field effect transistor with a leakage shielding structure can be prepared by the preparation method of the first embodiment, but is not limited to the preparation method of the first embodiment, as long as it can be formed The SOI field effect transistor with the leakage shielding structure is sufficient. For the beneficial effects achieved by the SOI field effect transistor with the leakage shielding structure, please refer to Embodiment 1, which will not be repeated below.

[0102] like Figure 2 to Figure 4 , Figure 35 to Figure 39 As shown, the SOI field effect transistor with leakage shielding structure includes:

[0103] A patterned SOI substrate 200 includes a bottom substrate 201, an insulating layer 202, and a top semiconductor layer 203, and the insulating layer 202 under the top semiconductor layer 203 has in the first direction and The groove 204 extendin...

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Abstract

The invention provides an SOI field effect transistor with a leakage shielding structure and a preparation method thereof, the structure comprising: a patterned SOI substrate having a bottom substrate, an insulating layer and a top semiconductor layer in the form of a semiconductor island, the insulating layer has grooves, The semiconductor island completely covers the groove; the heavily doped region of the first conductivity type is formed on both ends of the top semiconductor layer extending along the second direction above the groove, and its width in the second direction is greater than that of the top semiconductor layer located above the groove The width of the overlapping region of the top semiconductor layer and the insulating layer extending along the second direction; the gate structure is formed above the groove; the source region and the drain region of the second conductivity type are formed at both ends of the gate structure; the body bias An electrode is formed on the heavily doped region of the first conductivity type. By setting the heavily doped region of the first conductivity type and the body bias electrode, the height of the PN junction barrier formed by the channel inversion layer and the heavily doped region can be effectively adjusted, and the leakage channel caused by the total dose effect can be effectively eliminated, making the device Zero response to total dose effect.

Description

technical field [0001] The invention belongs to the field of semiconductor design and manufacture, in particular to an SOI field effect transistor with a leakage shielding structure and a preparation method thereof. Background technique [0002] The field effect transistor on the SOI substrate has a good anti-single event effect, but due to the SOI structure, the insulating layer (BOX layer) tends to accumulate more induced charges when high-energy particles are incident. A parasitic conduction channel is induced in the device, which induces leakage current and drifts the electrical performance of the device. This effect is called the total dose effect, and the total dose effect is the main reason for the failure of SOI transistors in the high-energy particle irradiation environment. SUMMARY OF THE INVENTION [0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a SOI field effect transistor with a leakage...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/06H01L29/423H01L29/786
CPCH01L29/0638H01L29/0684H01L29/4238H01L29/42376H01L29/66742H01L29/78603H01L29/78609
Inventor 刘强俞文杰
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI