Dynamic comparator circuit with low power consumption
A dynamic comparator, low-power technology, applied in multiple input and output pulse circuits, electrical components, pulse processing, etc., can solve problems such as reducing leakage current power consumption, high power consumption, and reducing circuit dynamic power consumption, etc. Achieve the effect of reducing dynamic power consumption, low power consumption, and reducing leakage current power consumption
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[0014] The technical scheme of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.
[0015] The present invention proposes a low power consumption dynamic comparator circuit, such as figure 2 As shown, it includes a bias module for providing DC bias. In this embodiment, the bias module adopts a bias transistor 201, which is the fourth NMOS transistor M1, and the gate of the fourth NMOS transistor M1 is connected to the clock The source of the signal CLK is grounded, and the drain is used as the output terminal of the bias module. The first NMOS transistor M2 and the second NMOS transistor M3 are input transistors 202, the first PMOS transistor M6 and the second PMOS transistor M7 are cross-coupled transistors 204, and the gate of the first NMOS transistor M2 is used as the positive input of the dynamic comparator circuit The terminal is connected to the positive input signal Vip, and its drain is connected to...
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