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Preparation method of semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device preparation, can solve problems such as increasing manufacturing costs, and achieve the effect of saving process costs and reducing photomask processes

Active Publication Date: 2021-05-28
晶芯成(北京)科技有限公司
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

In order to achieve this goal, the method of increasing ion implantation (ESD implant) in the drain area is often used to reduce the breakdown voltage of the ESD device, but increasing the ion implantation in the drain area requires an additional mask, thus increasing the manufacturing cost

Method used

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  • Preparation method of semiconductor device
  • Preparation method of semiconductor device
  • Preparation method of semiconductor device

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preparation example Construction

[0023] figure 1 A flow chart of a method for preparing a semiconductor device provided in this embodiment, such as figure 1 As shown, the preparation method of the semiconductor device provided in this embodiment includes:

[0024] S01: providing a semiconductor substrate, a gate is formed on the semiconductor substrate, and a source and a drain are formed in the semiconductor substrate on both sides of the gate;

[0025] S02: forming an interlayer dielectric layer on the semiconductor substrate;

[0026] S03: Etch the interlayer dielectric layer to respectively form contact holes connecting the gate, the source, and the drain, wherein the contact holes connecting the drain are strip-shaped, and continuously expose at least Part of the drain, the contact hole connecting the gate and the source is dot-shaped, and at least part of the gate and the source are intermittently exposed; and,

[0027] S04: Obliquely implanting ions into the interlayer dielectric layer from multiple...

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Abstract

The invention provides a method for preparing a semiconductor device, which includes providing a semiconductor substrate on which a gate, source and drain are formed, then forming an interlayer dielectric layer on the semiconductor substrate, and etching the interlayer dielectric Layers form contact holes, wherein the contact holes connected to the drain are strip-shaped, and at least part of the drain is exposed continuously, and the contact holes connected to the gate and source are in the form of points, and at least part of the gate and source are exposed intermittently. Then ions are obliquely implanted into the interlayer dielectric layer to ensure that ions in at least one direction are implanted into the drain electrode through the contact hole to form an ion implantation region. The present invention performs ion implantation through the contact hole in the interlayer dielectric layer to realize ESD protection. Compared with the prior art, a yellow light is made on the drain to define the ion implantation area before the interlayer dielectric layer, and the present invention reduces one step of photomask The process saves the cost of the process and is simple and easy to implement.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for preparing a semiconductor device. Background technique [0002] As semiconductor device technology continues to enter submicron and deep submicron, the reliability of ESD (electrostatic discharge) protection devices becomes more and more important. For MOS devices used as ESD protection, in order to achieve the purpose of internal circuit protection, the breakdown voltage of MOS devices used as ESD protection is often required to be slightly lower than the protected device, and the series resistance of the drain region is higher than that of the protected device. In order to achieve this goal, the method of increasing ion implantation (ESD implant) in the drain area is often used to reduce the breakdown voltage of the ESD device, but increasing the ion implantation in the drain area requires an additional mask, thus increasing the manufacturing co...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L21/336H01L21/265
CPCH01L21/26506H01L21/26513H01L21/26586H01L21/823418H01L29/66477
Inventor 陈明睿柯天麒詹奕鹏鲍贤贤郭千琦
Owner 晶芯成(北京)科技有限公司