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Fast and safe hardware multiplier for SM2 and application thereof

A multiplier and security technology, applied in the field of information security, can solve the problems of long operation time, complex hardware structure, no SM2 parameter design, etc., and achieve the effect of shortening the delay

Pending Publication Date: 2020-12-18
SHANGHAI JIAO TONG UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The hardware structure of the prior art is complicated, the calculation time is long, and the SM2 parameters are not designed effectively

Method used

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  • Fast and safe hardware multiplier for SM2 and application thereof
  • Fast and safe hardware multiplier for SM2 and application thereof
  • Fast and safe hardware multiplier for SM2 and application thereof

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Embodiment Construction

[0017] Such as figure 1 As shown, the present embodiment relates to a kind of multiplier that realizes Montgomery modular multiplication operation, including: multiplication and addition module, modular multiplication controller, register files and subtractors and some selectors for storing intermediate results of calculation, wherein: modular The multiplying controller and the first selector are all connected with the multiplying and adding module and input the state information state and the algorithm input data P respectively, and the multiplying and adding module performs (c, z)=a+ according to the input data A, B, P and the state information state The operation of xy+b and output the result to the register file, the register file outputs the intermediate result of data Z to the fourth selector, and outputs the intermediate data t i , c a , c b , v, Z to the multiplication and addition module, the subtractor outputs the calculation result Z-P and the borrow flag s to the...

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Abstract

The invention provides a fast and secure hardware multiplier for SM2 and application thereof, wherein the fast and secure hardware multiplier comprises: a multiply-add module, a modular multiply controller, a register file for storing a calculation intermediate result, and a subtracter, where: the multiply-add module comprises two independent multiply-add devices, each multiply-add device performs(c, z) = a + xy + b operation on 64-bit operands; the modular multiplication controller is connected with the multiply-add module and the register file and sends an execution instruction according toa clock period, the multiply-add module outputs a calculation intermediate result to the register file, and the output end of the register file is connected with the input end of the multiply-add module and the input end of the subtracter to achieve cyclic calculation and result output. And the output end of the subtracter and the output end of the register file are connected with an external interface to output a final result. According to the method, while the Montgomery modular multiplication operation delay can be greatly shortened, an effective protection means is adopted for side channel attack vulnerabilities existing in the algorithm, so that private data cannot be leaked while SM2 underlying operation is quickly executed, and the method has the characteristics of quickness and safety.

Description

technical field [0001] The invention relates to a technology in the field of information security, in particular to a fast and safe hardware multiplier for SM2 and its application. Background technique [0002] The existing Montgomery modular multiplication operation is an important link in the SM2 encryption calculation process, and its algorithm process is as follows: [0003] [0004] In the prior art, the hardware structure is complex and the calculation time is long, and the SM2 parameter is not effectively designed. [0005] By analyzing the algorithm, it can be seen that there is no data correlation between steps 5 and 6, and between steps 8 and 9, that is, the input value of the latter step does not depend on the calculation result of the previous step, so two independent multipliers can be used The adder is used to execute these steps in parallel, especially the parallel calculation of steps 8 and 9, which can reduce the calculation time of the inner loop by hal...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/72G06F21/60
CPCG06F7/728G06F21/602
Inventor 谷大武王腾飞陆海宁张海峰
Owner SHANGHAI JIAO TONG UNIV
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