Semiconductor memory devices and memory systems including the same

Abstract

The invention provides a semiconductor memory devices and memory systems including the same. The semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generationsignal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skipan ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2019-0072725 filed with the Korean Intellectual Property Office on June 19, 2019, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0003] The present disclosure relates to memory, and more particularly, to semiconductor memory devices and memory systems. Background technique [0004] Semiconductor memory devices can be classified into nonvolatile memory devices such as flash memory devices and volatile memory devices such as DRAM. The high-speed operation and cost efficiency of DRAM make it possible for DRAM to be used for system memory. As the manufacturing design rules of DRAMs continue to shrink, bit errors of memory cells in DRAMs may increase rapidly, and yields of DRAMs may decrease. Contents of the invention [0005] According to some example embodiments, a semiconductor memory device may incl...

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Problems solved by technology

Due to the continued shrinking of DRAM manufacturing design rules, bit errors of memory cells in DRAM may increase rapidly, and the yield of DRAM may decrease

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