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MDAC for driving the push-pull output stage of GS/s pipeline ADC

A push-pull output and output terminal technology, applied in the field of mixed-signal integrated circuit design, can solve the problems of difficult sampling rate, long operation amplifier settling time, affecting the stability of the operational amplifier, etc., and achieve the effect of reducing load capacitance and shortening the settling time

Active Publication Date: 2020-12-29
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Pipeline ADC is a common structure to realize high-speed and high-precision ADC. In this structure, the output terminal of the first-stage MDAC will be connected to the load capacitor CL, which is also a pipeline The sampling capacitor of the second stage of the ADC, the operational amplifier directly drives the load capacitor CL, because the capacitive drive capability of the transconductance operational amplifier is not good, and the capacitance of the load capacitor CL is very large, generally on the order of hundreds of fF, which will not only make the The long settling time of the op amp may also affect the stability of the op amp, making it difficult to further increase the sampling rate

Method used

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  • MDAC for driving the push-pull output stage of GS/s pipeline ADC
  • MDAC for driving the push-pull output stage of GS/s pipeline ADC
  • MDAC for driving the push-pull output stage of GS/s pipeline ADC

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Embodiment 1

[0021] like figure 1 and if figure 2 As shown, an MDAC applied to the GS / s pipeline ADC push-pull output stage drive provided by the embodiment of the present invention includes a quantization module, a residual amplification module and a load capacitor CL, and the quantization module is used for quantization and operation to generate quantization As a result and the unamplified residual signal, the residual amplification module is used to amplify the residual signal and drive the load capacitor CL, wherein the residual amplification module includes: an inverting amplifier and a pushing A pull output stage circuit, the output end of the quantization module is connected to the input end of the inverting amplifier, the input end of the push-pull output stage circuit is connected to the output end of the inverting amplifier, and the push-pull output stage The circuit includes: first capacitor C1, second capacitor C2, first resistor R1, second resistor R2, first MOS tube M a an...

Embodiment 2

[0028] like figure 2 As shown, on the basis of Embodiment 1, the inverting amplifier in the embodiment of the present invention is composed of a full-complementary common-source positive feedback high-speed amplifier, figure 2 Shows the structural diagram of a fully complementary common-source positive feedback high-speed amplifier. The inverting amplifier is composed of two complementary common-source positive feedback operational amplifiers, a third capacitor CS, and a fourth capacitor CF. The two-stage complementary common-source The positive input terminals of the first-stage complementary common-source positive feedback operational amplifier in the positive positive feedback operational amplifier are respectively connected to one end of the third capacitor CS and one end of the fourth capacitor CF, and the other end of the third capacitor CS Connected to the output of the quantization module, the output terminal of the first-stage complementary common-source positive fe...

Embodiment 3

[0031] like image 3 and Figure 4 As shown, the two complementary common-source positive feedback operational amplifiers provided by the embodiment of the present invention, wherein the first-stage complementary common-source positive feedback operational amplifier is as image 3 As shown, the second-stage complementary common-source positive feedback operational amplifier is as Figure 4 , any of the two complementary common-source positive feedback operational amplifiers includes: the third MOS transistor M0, the fourth MOS transistor M1, the fifth MOS transistor M2, the sixth MOS transistor M3, the seventh MOS transistor M4, the eighth MOS transistor M5, the ninth MOS transistor M6, and a common-mode feedback circuit, the output end of the common-mode feedback circuit is connected to the gate of the third MOS transistor M0, and the third MOS transistor M0 The source of the power supply is connected to the positive pole VDD of the power supply, the drain of the third MOS ...

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Abstract

The embodiment of the invention provides a high-speed MDAC for driving a push-pull output stage of a GS / s pipeline ADC. The push-pull output stage is added between the output end of an operational amplifier and the second stage of the pipeline ADC, and a push-pull output stage circuit is added to isolate the operational amplifier from the second-stage sampling capacitor of the pipeline ADC, so theload capacitance driven by the operational amplifier is reduced. And in addition, the push-pull output stage circuit has the characteristic of high capacitive load driving capability, so the push-pull output stage circuit can quickly establish a residual error signal transmitted by the operational amplifier on a second-stage sampling capacitor of the pipeline ADC. Compared with a conventional structure that an operational amplifier is directly connected with a second-stage sampling capacitor of an assembly line, the overall MDAC establishing time is shortened, and high-speed MDAC is achieved.

Description

technical field [0001] The invention relates to the field of mixed-signal integrated circuit design, in particular to an MDAC applied to GS / s pipeline ADC push-pull output stage drive. Background technique [0002] Pipeline ADC is a common structure for realizing high-speed and high-precision ADC. In this structure, the output terminal of the first-stage MDAC is connected to the load capacitor CL, which is also the sampling capacitor of the second-stage pipeline ADC. The op amp directly drives the load capacitor CL. , because the capacitive driving capability of the transconductance op amp is not good, and the capacitance of the load capacitor CL is generally on the order of hundreds of fF, which will not only make the settling time of the op amp very long, but also may affect the stability of the op amp However, it is very difficult to further increase the sampling rate. [0003] In view of this, the present invention proposes a high-speed MDAC driven by a GS / s pipeline pu...

Claims

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Application Information

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IPC IPC(8): H03M1/14
CPCH03M1/145
Inventor 刘马良张晨曦张乘皓朱樟明杨银堂
Owner XIDIAN UNIV