Heat dissipation control circuit, heat dissipation back splint and mobile terminal
A control circuit and control terminal technology, applied in the direction of electrical components, telephone structures, electrical equipment components, etc., can solve the problems of single structure, limited heat dissipation effect, bad experience, etc., to achieve the effect of enhancing heat dissipation performance and improving user experience
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Embodiment 1
[0049] image 3 It is the first circuit diagram of the first embodiment of the heat dissipation control circuit of the present invention. This embodiment proposes a heat dissipation control circuit, which includes: PMOS transistor Q1, NMOS transistor Q2, PMOS transistor Q3, NMOS transistor Q4, and NMOS transistor Q5, wherein the source and gate of the PMOS transistor Q1 A resistor R1 is connected in parallel, the gate of the PMOS transistor Q1 is connected to the control terminal of the power supply chip, the source of the NMOS transistor Q2 is connected to the positive pole of the fan, the drain of the NMOS transistor Q2 is grounded, and the drain of the NMOS transistor Q2 The gate is connected to the control terminal, the source of the NMOS transistor Q2 is connected to the power supply terminal of the power chip, the gate of the NMOS transistor Q2 is connected to the source of the NMOS transistor Q5, and the PMOS transistor The drain of Q3 and the source of the NMOS transi...
Embodiment 2
[0052] Figure 4 It is the second circuit diagram of the second embodiment of the heat dissipation control circuit of the present invention. Based on the above embodiment, optionally, if the control terminal outputs a low level (L), the gate of the PMOS transistor Q3 is at a low level, The PMOS transistor Q3 works in an on state, the power terminal outputs to the anode through the PMOS transistor Q3, the gate of the NMOS transistor Q2 is at a low level, and the NMOS transistor Q2 works in an off state, so The power supply voltage of the positive pole is provided by the power supply terminal.
[0053] Optionally, the source of the NMOS transistor Q5 is pulled up to the power supply terminal by the pull-up resistor R2, the gate of the PMOS transistor Q3 is at a high level, and the PMOS transistor Q3 works in an off state, so The power supply terminal no longer outputs to the positive pole through the PMOS transistor Q3.
[0054] Optionally, the gate of the NMOS transistor Q4 i...
Embodiment 3
[0057] Figure 5 It is the third circuit diagram of the third embodiment of the heat dissipation control circuit of the present invention. Based on the above embodiment, optionally, if the control terminal outputs a high level, the gate of the PMOS transistor Q3 is at a high level, and the PMOS The transistor Q3 works in a cut-off state, and the power terminal no longer outputs to the positive pole through the PMOS transistor Q3.
[0058] Optionally, the gate of the NMOS transistor Q2 is at a high level, the NMOS transistor Q2 works in a conduction state, and the power supply voltage of the anode is a ground voltage.
[0059] Optionally, the gate of the NMOS transistor Q5 is at a high level, the NMOS transistor Q5 works in a conduction state, the source of the NMOS transistor Q5 is at a low level, and the gate of the PMOS transistor Q3 is at a low level , the PMOS transistor Q3 works in a conduction state, and the power terminal outputs to the negative electrode through the P...
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