Wafer test system and wafer test method

Abstract

The invention provides a wafer test system and test method, and the system comprises a probe card, an ARM processor, and a main control unit, which are sequentially connected together, and the probe card is provided with at least two contacts; the ARM processor monitors the test state information of each contact and transmits the test state information to the main control unit; meanwhile, a start-stop command of the main control unit is received so as to control opening, pausing or ending of each contact; the main control unit obtains a start-stop command according to the test state information, wherein the start-stop command comprises the following steps: controlling the contact pause of the previous test item until all contacts complete the test of the previous test item, and opening allcontacts to carry out the current test item; controlling the contacts finishing the current test item to pause until all the contacts finish the test of the current test item, and opening all the contacts to carry out the next test item; and controlling all contact end tests. Through synchronous completion of test items among different contacts, it is ensured that different contacts are located in the same test item at the same time, the wafer test precision is enhanced, and the test yield is improved.

Description

technical field [0001] The invention relates to the field of semiconductor testing, in particular to a wafer testing system and a wafer method. Background technique [0002] The process of semiconductor manufacturing generally includes integrated circuit design, wafer manufacturing, wafer testing, wafer cutting, chip packaging and finished chip testing. Among them, the wafer test is a test after the wafer manufacturing is completed, which is used to verify whether each chip (DIE) on the wafer meets the device characteristics and other design specifications. After the wafer test, the functional Defective chips are picked out in advance to prevent these chips from entering the later chip packaging steps. Wafer refers to the wafer used in the production of semiconductor integrated circuits. Its shape is circular, so it is called a wafer. Various circuit element structures can be processed on the wafer, and it becomes an IC product with specific electrical functions. The techn...

AI Technical Summary

Problems solved by technology

The existing conventional method is that all the joints in the wafer test are tested independently and sequentially at the same time. Different joints do not consider what test items are being performed by each other, and whether they will interfere with each other and cause measurement deviations.

Because the production quality of different tested chips is different and / or the process running speed of the test joints to which the tested chips belong is different, the test time of different joints of the wafer test is quite different, so that when different joints test different test items, there will be Mutual interference occurs, resulting in yield loss

For example, when some contacts on the wafer are testing high-voltage and high-current test items, and some contacts are testing low-voltage and low-current test items, that is, different nodes are in different test items at the same time. It will be affected by the EMI of the test item signal with high voltage and high current, and the measurement error will cause the wafer test result to over kill, that is, the chip that should have passed the test is tested as failed, resulting in a loss of yield.

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