A VLSI Impedance Network Model Extraction Method and System

Abstract

The invention relates to a method and system for extracting a VLSI impedance network model. The method includes performing grid division on the layout of the multi-layer integrated circuit to obtain a triangular grid; sequentially encoding the preset ports; obtaining the weighted distance from the grid node to the port in the triangular grid; if the weighted distance is greater than the weighted distance threshold, then retain the grid nodes of the triangle grid corresponding to the weight distance; use the weight distance corresponding to the retained grid nodes to encode the retained grid nodes; according to the encoding information of the retained grid nodes, use the finite element method Write the potential field equation of the integrated circuit to obtain the finite element sparse matrix; according to the coding of the grid nodes of the finite element grid, use the triangle-star transformation to eliminate the grid nodes of the finite element sparse matrix that are not ports, and obtain the multi-port network guide admittance matrix; extracts impedance network models from multiport network admittance matrices. The invention not only ensures the calculation accuracy but also reduces the calculation time.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method and system for extracting a VLSI impedance network model. Background technique [0002] The conventional method of extracting the impedance network model of multilayer VLSI is the simplified transmission line method, or the field-based calculation method to calculate the S-parameter matrix of VLSI, and then convert it into the impedance network model of integrated circuit based on the S-parameter matrix. The calculation speed of the above transmission line method is fast, but due to the large approximation of the layout of the integrated circuit, the calculation results of the layout with a simple structure and rules in the early stage of processing are accurate, but in recent years, the structure has become more and more complex and the scale range is centimeters. Layouts down to the nanometer level produce incomparable errors. The latter method is calculated based o...

AI Technical Summary

Problems solved by technology

This method can give very accurate calculation results for the complex layout structure of integrated circuits, but it takes a long time to solve the entire sparse matrix, and after obtaining the field distribution, an additional process is required to calculate the S parameter matrix and convert it into impedance Therefore, this method takes a long time to calculate and the process is complicated, and there will be inevitable errors in the calculation of the S parameter matrix and the conversion of the S parameter matrix into the impedance network model.

[0003] The calculation time is reduced by eliminating grid nodes. However, for multi-layer VLSI, the number of layers reaches dozens of layers, and the layout scale ranges from centimeters to nanometers. For such a complex multi-scale structure, in When the unstructured grid is used, the number of units and unknowns generated reaches tens of millions or even hundreds of millions. If all the units are eliminated, the calculation time is also very long

Images