A kind of digital processing circuit based on fpga which combines integration and high-pass filtering
A technology of high-pass filtering and digital processing, applied in the direction of digital technology network, electrical components, impedance network, etc., to achieve the effect of saving FPGA resources, avoiding the difficulty of realizing high-speed pipeline design, and avoiding DC bias problems
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Synchronous outputs to the first and second multipliers.
Described first floating-point multiplier is used to carry out operation to the output numerical value of first register and parameter selector, real
c in the formula
2
*y(n‑2), and output the operation result to the first adder.
Described second floating-point multiplier is used to carry out operation to the output numerical value of first register and parameter selector, real
c in the formula
1
*y(n‑1), and output the operation result to the second adder.
Described control circuit mainly comprises two counters and some sequential logic and reset logic, for controlling
The output time of the FIFO result in the entire integrating high-pass hybrid circuit, the data input time of the first adder and the second adder
and the extraction time of the output result of the calculation and the reset and initialization time of these two adders. The control circuit also implements the
The calculation result of t...
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