System for achieving data processing acceleration based on FPGA and acceleration method thereof

Abstract

The invention discloses a system for achieiving data processing acceleration based on an FPGA and an acceleration method thereof. The system comprises: an SRIO bus module; an SRIO multi-channel DMA interface module; a DMA module; a user acceleration algorithm module; a SerDers module; and an optical fiber module. The method comprises the following steps: step 1, achieving a user acceleration algorithm module; step 2, achieving an SRIO bus module; 3, achieving a DMA module; 4, enabling the DMA module to perform data flow direction control management; and 5, connecting the plurality of DMA modules with the plurality of user acceleration algorithm modules in a one-to-one correspondence manner. According to the system and the acceleration method thereof, a hardware acceleration function is achieved through programmable logic, so that a highly customized data processing requirement can be met, and a data processing task is achieved by using a gate-level circuit, so that the processing speedcan be greatly increased; in addition, the FPGA chip is directly connected with the processor through the SRIO bus, and compared with a PCIe bus, the FPGA chip has more flexible data transmission andtopological configuration.

Description

technical field [0001] The invention relates to the technical field of circuit design, in particular to a FPGA-based data processing acceleration system and an acceleration method thereof. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. The device was first launched by Xilinx in 1985. It is a A new type of high-density PLD, manufactured by CMOS-SRAM technology. The structure of FPGA is divided into three parts: configurable logic module CLB (Configurable Logic Block), input and output module IOB (Input Output Block) and internal wiring (Interconnect), there are many configurable logic units (LE, LogicElement) inside FPGA , users can realize different logic functions by on-site programming of these configurable modules. Compared with ASICs, FPAG has higher flexibility, shorter development cycle, FPGA can be programme...

AI Technical Summary

Problems solved by technology

[0004] The PCIe bus must have visibility to the address space of the target device before it can read and write to the address space of the target device, which will lead to inflexible data transmission;

[0005] In the PCIe bus protocol, each device shares a PCIe address space. If in the tree structure, each device is assigned an address space in the entire address space mapping, it is necessary to perform all address decoding to find the device. In device systems with large-capacity memory, this device addressing mechanism is not suitable for flexible topology expansion of hardware accelerators

Images