A kind of low conduction resistance MOS device and preparation technology

Abstract

The invention discloses a low on-resistance MOS device and a preparation process, which belong to the technical field of semiconductor manufacturing, comprising: respectively etching and forming a first deep groove and a second deep groove in a well region, respectively forming a first deep groove and a second deep groove at the bottom of the first deep groove; Implanting to form a first source region, implanting at the bottom of the second deep trench to form a second source region, respectively filling the first metal layer in the first deep trench and the second deep trench; and etching in the dielectric layer to form a window to expose The first deep groove and the second deep groove; the second metal layer is deposited in the first window and the second window, and the substrate layer is thinned; the beneficial effect is: a recessed source electrode is formed by deep hole etching, The distance between the source and the drain is shortened, and the on-resistance of the MOS transistor is reduced while maintaining the device wafer within a safe thickness range, thereby reducing the wafer fragmentation rate, improving the product yield, and reducing production. cost.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a low on-resistance MOS device and a preparation process. Background technique [0002] MOS devices are widely used in various power management and switching conversions due to their high integration, low on-resistance, fast switching speed, and low switching loss. As one of the key parameters of MOS devices, on-resistance is its Further reduction has been the relentless goal of device design engineers. [0003] In the prior art, the on-resistance of MOS devices is mostly reduced by thinning the back side. However, due to the limitations of the semiconductor manufacturing process, the thinner the wafer is in the thinning process, the more likely the risk of fragmentation will occur, resulting in a large amount of economical damage. loss. How to reduce the on-resistance without fragmentation has become a difficult problem for every engineer. For example, in ...

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Problems solved by technology

For example, in the existing process, the number of sheet resistances from the D terminal to the S terminal of the MOS transistor is reduced by thinning the back of the wafer to reduce the on-resistance of the MOS transistor, but such a method needs to thin the wafer to About 80-100μm, the wafer fragmentation rate at this thickness is high, and the yield is low, which in turn pushes up the manufacturing cost

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