117 results about "Fragmentation rate" patented technology

The invention discloses a medium chromium multielement alloy cast ball and cast segment oil quenching heat treatment technique, wherein the contained components are as follow: 1.7-3.1 of C, 0.3-1.0 ofSi, 0.3-1.0 of Mn, 5-10 of Cr, less than or equal to 0.09 of S, less than or equal to 0.08 of P, and trace of Mo, Ni, Nb, Cu, Y, B, V and Ti; cast medium chromium multielement alloy cast ball and cast segment are heated to 930-1050 DEG C, the temperature is kept for 1.5-3h followed by oil cooling treatment, when the surface temperature of medium chromium multielement alloy cast ball and cast segment are decreased to 100-250 DEG C, the product is moved off the oil tank to halt oil quenching, and the product is poured into an iron bucket, when the iron bucket is full the product is put into a tempering furnace for tempering treatment. The invention solves the problem of poor use quality as cast condition of the medium chromium multielement alloy cast ball and cast segment, in addition, theproduct has no crack, the hardness, toughness and antifatigue impact service life is improved, consumption is reduced, and the ball fragmentation rate is low, thus saving quantities of chromium alloyresource for the nation and reducing operation cost for the user.

The invention discloses a high-power planar junction bidirectional TVS diode chip and a production method thereof, and relates to the technical field of manufacturing of a semiconductor device. The production method comprises the following steps of: protecting both surfaces of a silicon wafer with SiO2; photo-etching diffusion windows on the both surfaces; simultaneously forming P-type diffusion regions in the diffusion windows; and forming coated regions on the surfaces of the P-type diffusion regions. By adopting shallow junction diffusion, the process has the advantages of short diffusion time, long product life, high performance, no warping of the silicon wafer and low fragmentation rate of the product. Trenching is not needed during the production, so the utilization ratio of the silicon wafer and the current density of the product can be improved. Scribing is not performed on a glass passivation layer, so the stress of a glass passivation film can be prevented so as to contribute to ensuring firm structure, reducing leakage current, particularly the leakage current at the high temperature and improving the reliability of the product. By using a multilevel metallization mode, the coating can be finished at one time and has simple process and high reliability.

The invention relates to the technical field of crystalline silicon cell manufacturing, and discloses a cell splitting device and a cell splitting method. The device comprises a device body, a feeding device and a flexible belt conveying device which are arranged on the device body in sequence, a lifting device mounted on the device body and disposed at one side of the flexible belt conveying device, a flexible belt coating device mounted on the lifting device and disposed on the upper end of the flexible belt conveying device, and a roller rolling device mounted on the lifting device and disposed on the upper end of the flexible belt coating device. A pressing device for driving the roller rolling device to press the flexible belt coating device and a linear moving device for driving the roller rolling device to move along the conveying direction of the flexible belt conveying device are mounted on the roller rolling device. According to the invention, a cell is coated with two layers of flexible belts and is rolled by the roller rolling device, so that the cell is not broken or moved, the efficiency of cell splitting is improved, and the fragmentation rate is reduced.

The invention provides an auxiliary chemical composition used for monocrystalline silicon or polycrystalline silicon acidic texturization. The auxiliary chemical composition includes: polysaccharide or its derivative, polyol or its derivative. The preparation and use method of the auxiliary chemical composition is simple and easy to implement, and has good repeatability. When used for diamond wire-cut monocrystalline silicon or polycrystalline silicon texturization, the auxiliary chemical composition can increase the texturization temperature, and at the same time can greatly improve the surface texturization uniformity, and the prepared silicon chip has the characteristics of low reflectivity, clean surface, low fragmentation rate, and uniform color after coating, thus greatly improving the photoelectric conversion efficiency of silicon cells.

An apparatus for managing memory in a real-time embedded system and a method of allocating, deallocating and managing memory in a real-time embedded system. The apparatus includes a defragmentation unit performing a defragmentation task according to a predetermined priority to collect together memory fragments, and a memory manager allocating or deallocating a predetermined area of memory upon request of a task, and calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task. The method of managing memory in a real-time embedded system includes determining whether the conditions under which the memory is used vary, and if the condition vary, calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task according to the memory fragmentation rate.

The invention relates to a manufacturing technique of a chip for a two-way voltage regulator diode DB3, wherein the two-way voltage regulator diode DB3 is a symmetrical diode with the structure of N<+> PN<+>. The resilience voltage is increased due to the adoption of a triple photolithographic process, the trigger capacity of the two-way voltage regulator diode is improved; due to the application of shallow mesa or trench etching, the fragmentation rate is reduced; and glass is passivated due to the adoption of an electrophoretic process, the withstand voltage stability and reliability of the two-way voltage regulator diode are improved. The manufacture technique of the chip for the two-way voltage regulator diode has the advantages of improving the breakdown voltage stability of the two-way voltage regulator diode DB3, enhancing the trigger capacity of the diode, reducing the high-temperature power consumption, prolonging the service life of the diode, and simultaneously improving the qualification rate.

The invention discloses a Linux platform physical memory information monitoring system, which can monitor use conditions of physical memories under a Linux platform and optimize use of Linux platform physical memory resources. By adoption of the means of kernel patching and a memory monitoring processing module, static monitoring and dynamic monitoring of overall conditions and detailed use conditions of the physical memories in the Linux platform can be performed and monitoring of the following physical memory information in the Linux platform is realized, for example, acquisition of the number of distributive designated stage memory blocks, acquisition of memory details to compute external fragmentation rate of the memories and so on, thereby the invention has good compatibility and suitability. The system of the invention is particularly suitable for an embedded type Linux platform, wherein, various memory resources are limited but complex memory operations are needed to be provided.

The invention discloses a method for packaging a solar module, comprising the serial connection of cell slices. A method for the serial connection of the cell slices is as follows: a traditional thin welding tape is welded and connected with a front electrode of one cell slice, then the welding tape is led from the front face to the back face of the other cell slice, and finally the welding tape and a back electrode of the cell slice are spliced together by a conducting adhesive tape. The method for packaging a solar module adopts the conducting adhesive tape to replace the traditional welding tape for the connection between every two cell slices, using no welding processes or less welding processes, thereby greatly lowering the fragmentation rate caused by bow action , greatly reducing the possibilities of subfissure and back electrode damage, improving the module conversion efficiency, saving the raw materials and lower the module packaging cost.

The invention provides a method for laying a photovoltaic module. The method comprises the following steps of: a) evaporating and plating a solder strip and a bus bar on a glass plate in vacuum; b) welding a battery plate set to the solder strip and the bus bar by using laser to obtain the glass plate welded with the battery plates; c) laying an EVA plate on the battery plate set; and d) laying a back plate on the EVA plate to obtain the laid battery plate. By using the method for laying the photovoltaic module provided by the invention, the glass plate and the battery plate are integrated into a whole; the glass plate is bonded to the battery plate without needing EVA; the thickness of the photovoltaic module is reduced; moreover, the fragments of the battery plate can be detected by using infrared ray after laying and the fragments do not need detecting again after lamination and formation, so that fragmentation rate is reduced and the controllability of the quality of the photovoltaic module is increased.

The invention discloses a double-surface continuous series welding system for a fragile crystal silicon chip and a welding method thereof. An upper fixing plate is arranged on the upper side of a bracket of the system; an upper welded component and a drive motor that drives the upper welded component to conduct parallel movement are arranged on the upper fixing plate; a transport mechanism that supports and transfers the welded crystal silicon chip is arranged on the lower side of the upper welded component on the bracket; an upper locating component for locating an upper welded crystal silicon chip and a solder strip is arranged on the upper side of the transport mechanism; a lower fixing plate is arranged on the lower side of the bracket corresponding to the upper side thereof; a lower welded component symmetrical to the upper fixing plate, and a drive motor that drives the lower welded component to conduct parallel movement are arranged on the lower side of the bracket; and a lower locating component for locating a lower welded crystal silicon chip and a solder strip is arranged on the lower side of the transport mechanism on the bracket. The welding method comprises the following steps: the crystal silicon chips are arranged; the solder strips are installed; each welding component operates; the solder strips are welded on the silicon chips by a welding device; after welding, the previous welded crystal silicon chip is removed and replaced by a new crystal silicon chip for continuous welding. The invention reduces the fragmentation rate and ensures high welding efficiency.

The invention relates to a marking method for ingot casting polycrystalline silicon slice head and tail sequencing, which comprises the following steps: 1) detecting: carrying out infrared and minority carrier lifetime detection on a squarely holed ingot casting polycrystalline silicon crystal bar; 2) cutting off: determining the cut-off position according to the infrared and minority carrier lifetime detection results so as to carry out cut-off processing; 3) marking: utilizing laser to draw lines for marking on the surface of the cut-off crystal bar; 4) surface burnishing: burnishing the surface of the marked crystal bar for polishing; 5) chamfering: chamfering the crystal bar after surface burnishing; 6) bar sticking: sticking the chamfered crystal bar onto a crystal holder through curing adhesive; and 7) slicing: curing the crystal bar for a period of time and then sending the crystal bar into a stock for slicing. The ingot casting polycrystalline silicon bar is sliced after being marked in the method disclosed by the invention, and finally the heads and tails of silicon slices are sequenced according to the positions of line marks at the edges of the silicon slices, so the positions of the silicon slices in the crystal bar can be clearly identified, and the fragmentation rate is not increased.

The invention discloses a graphite boat for a crystalline silicon solar energy PERC battery and a saturation process thereof, wherein the graphite boat comprises a graphite boat body, and SiC films are plated on all surfaces of the graphite boat body. A SiC film is plate on that graphite boat in the graphite boat saturation process of the invention, The SiC film has good corrosion resistance, so it will not be corroded by nitrous oxide in the back passivation process, and the surface of the graphite boat can be smooth, which not only protects the graphite boat, prolongs the service life of thegraphite boat, but also ensures the uniformity of the back passivation film and reduces the fragmentation rate. At the same time, due to the excellent wear resistance of SiC film, the EL scratch caused by friction can be reduced, and the subsequent saturation process time is greatly shortened, so that the productivity of the machine is improved.

The invention discloses a blasting fragmentation prediction method based on a cart tree regression algorithm. A CART decision tree model is constructed and trained by a CLS algorithm using the existing historical rock fragmentation related parameters as sample attributes. New rock fragmentation related parameters are collected and forecasted by the trained CART decision tree model. In accordance with that prior art, the invention firstly constructs a CART decision tree model and trains the CART decision tree model according to the related parameters of the historical rock fragmentation, then,the trained CART decision tree model can be used for predicting the blasting fragmentation. The invention prevents the occurrence of the blasting fragmentation accident from the root cause, reduces the large fragmentation rate generated in the blasting process, reduces the secondary fragmentation, improves the production efficiency and saves the blasting cost.

The invention discloses a welding method of a photovoltaic module. The welding method comprises the steps of: placing a conductive tape between a welding strip and a main grid line of a battery piece, wherein the conductive tape is a metal foil or a piece of conductive cloth with two sides being provided with conductive back adhesive, and the melting temperature of the conductive back adhesive is below 400 DEG C; heating to enable the conductive back adhesive to be melted so as to bond the welding strip with the main grid line of the battery piece; and cooling to complete the welding process. During the welding process, the welding strip and the battery piece are bonded with each other by using the conductive tape, the temperature during the process is below 400 DEG C which is the welding temperature of the welding strip and the battery piece in the prior art, and the welding temperature in the welding process is lower than the welding temperature in the prior art to realize low-temperature bonding so as to relieve the phenomenon of uneven expansion and shrinkage between the welding strip and the battery piece, thus reducing stress generated in the welding process, and reducing the battery fragmentation rate in the welding process of the photovoltaic module. The invention also provides the photovoltaic module produced by using the welding method.

The invention discloses an automatic sand blasting device used for diamond wire polycrystalline silicon slices. The automatic sand blasting device comprises a starting system, a grinding fluid system, a spray gun system, a feeding system, a process bin and a controller. When an operation command input from the outside is a sand blasting command, the controller automatically controls the starting system, the grinding fluid system, the spray gun system and the feeding system to conduct sand blasting treatment on the surfaces of the diamond wire polycrystalline silicon slices. The automatic sand blasting device is easy to operate, high in processing precision and processing stability, low in fragmentation rate and high in production capacity. The surfaces of the diamond wire polycrystalline silicon slices are subjected to sand blasting treatment, and consequently the surface microtopography of the diamond wire polycrystalline silicon slices can be changed; and the diamond wire polycrystalline silicon slices subjected to surface treatment can be directly used for production of battery pieces.

The invention provides a shared memory optimization processing method and device based on a multipath processor. The shared memory optimization processing method based on the multipath processor is characterized by comprising the steps that data structure modification is conducted on a Linux kernel in a multipath processor environment, wherein data structure modification comprises the step of additionally arranging a data structure chain table in a free_area data structure; block allocation optimization is conducted on a block allocation algorithm of a shared physical memory in the multipath processor environment according to the modified free_area data structure; block release optimization is conducted on a block release function according to the modified free_area data structure. Compared with an existing partner algorithm, the method and device have the advantages that time consumption can be reduced, the usage efficiency of the physical memory is promoted, and the memory fragmentation rate is decreased.

The invention provides a preparation method of an MWT solar cell. According to the method, the production technical scheme of a double-sided MWT + cell is provided to ensure the basic conversion efficiency and cost advantages of the MWT + cell. The MWT + aluminum grid double-sided cell technology is applied to reduce the warpage problem caused by the sheet so that the fragmentation rate of the cell and the assembly process can be reduced; meanwhile, the MWT + double-sided cell technology effectively improves the conversion efficiency of the cell.

The invention discloses a preparation method for back contact type silicon solar cell, which comprises the following steps of: (1) etching texture on the illuminated surface of silicon chips, and setting holes; (2) coating, diffusing and forming junctions on the illuminated surface of the silicon chips; forming PN junctions on the illuminated surface and in the holes; (3) setting transparent heat conducting film on the PN junctions on the illuminated surface and in the holes; (4) etching the circumference; plating antireflection films on the transparent heat conducting film on the illuminated surface of silicon chips; and (5) preparing through hole electrode, back metal electrode and back passivation field on the non-plating film surface of the silicon chips to obtain the back contact type silicon solar cell; and the through hole electrode is electrically communicated with the transparent conducting film. The illuminated surface of the back contact type silicon solar cell is not covered by electrode, so shading loss is avoided and the photoelectric conversion efficiency is greatly improved. The quantity of to-be-opened holes is greatly reduced so as to dramatically reduce the fragmentation rate and simplify the preparation processes.

The invention relates to a solar cell sheet EL defect testing machine, which includes a rack, a conveying mechanism mounted on the rack and a feeding mechanism, a test mechanism and a blanking mechanism arranged in order; A feeding mechanism includes at least one first horizontal linear module, at least one storage mechanism and at least one first vacuum adsorption mechanism; the storage mechanismis located on one side of the conveying mechanism, a first vacuum suction mechanism is mounted on the first horizontal linear module, the test mechanism comprises a camera assembly, a lifting mechanism, a probe assembly and a copper plate assembly mounted on the lifting mechanism, the probe assembly and the copper plate being arranged opposite each other in the vertical direction; the blanking mechanism comprising at least one second horizontal linear module, at least one second vacuum suction mechanism and a sorting assembly; the second vacuum suction mechanism being mounted on the second horizontal linear module. The invention is suitable for mass sampling inspection and full inspection of EL defects of battery sheets. The test speed is fast, lthe fragmentation rate is low; the invention can adopt to customers with different needs, is high in test efficiency, and has Extensibility.

The invention discloses a silicon wafer fully-automatic feeding/discharging manipulator and a movement trajectory control method thereof. The silicon wafer fully-automatic feeding/discharging manipulator and the movement trajectory control method thereof are used for fully-automatic feeding/discharging in multi-channel chain-type texturing, chain-type cleaning and sintering devices. The manipulator of the invention comprises a mounting base, a shoulder joint, a big arm, a small arm and a gripper used for gripping silicon wafers to multichannel solar battery sheet process equipment; the swing of the big arm and the small arm is controlled through a motor, and parametric design and PID control are adopted to realize concise control of the movement trajectory of the manipulator. With the silicon wafer fully-automatic feeding/discharging manipulator and the movement trajectory control method thereof of the invention adopted, problems such as large occupied space, complex mechanism, low flexibility, slow response and high production cost of chain-type texturing, chain-type cleaning and sintering devices as well as problems of serious wear of silicon wafer surface, low conversion efficiency and high fragmentation rate can be solved.

The invention relates to a method and a device for reducing fragmentation rate by chain type texturing for multicrystalline solar cells, a driving roller and limiting rollers are designed in a split manner, and the design of the limiting rollers leads the stress direction of a silicon wafer to be conductive to centralized transmission of the silicon wafer; the limiting rollers are arranged in thedirections which are vertical to the transmission direction of the silicon wafer, each limiting roller freely rotates around a shaft line thereof, when the silicon wafer touches the rollers, the generated friction force leads each roller to rotate around the shaft line thereof and leads the silicon wafer to move to a central line of the transmission; as the limiting rollers are arranged on both sides of the silicon wafer, the silicon wafer can move to the direction of the central line of the transmission no matter which side of the limiting rollers are touched by the silicon wafer, thereby playing the role of automatic deviation correction. The device has the advantages that the device changes the integral design of a conveying roller and the limiting rollers of the original scheme, removes alternating shear stress generated by friction of the limiting rollers and the silicon wafer, reduces an incentive of fragmentation of the silicon wafer and reduces the fragmentation rate to be within 2 per mill.