Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof. The method comprises the steps: forming a first initial gate electrode structure on a substrate, etching the side wall of the bottom of the first initial gate electrode structure, and enabling the first initial gate electrode structure to form a first gate electrode structure, wherein a first channel region is arranged in the substrate at the bottom of the first gate electrode structure, and the bottom size of the first gate electrode structure is smaller than the top size of the first gate electrode structure in the length direction of the first channel region. Since the size of the first initial gate electrode structure in the length direction of the first channel region is relatively large,the size uniformity of the first initial gate electrode structure can be well controlled in the process of forming the first initial gate electrode structure. The first gate electrode structure is formed by etching the side wall of the bottom of the first initial gate electrode, so that the formed first gate electrode structure is relatively good in size uniformity, the size uniformity of the device is improved, and the performance uniformity of the device is further improved.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method of forming thereof. Background technique [0002] In semiconductor manufacturing, with the development trend of large scale integrated circuits, the integrated circuit feature size continues to decrease. In order to form a smaller feature size, the photolithography technique is typically used for patterning. [0003] As the semiconductor process node continues to decrease, the self-aligned doublepatterning, SADP method and self-aligned quadrule patterning, SAQP approach have become favored in recent years. The method, the method can overcome the lithographic resolution limit of the photolithography process, and increase the density of the graphic formed on the substrate, further reduce the feature size of the graph. [0004] However, the uniformity of the components and performance uniformity of these methods are still y...

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Problems solved by technology

[0004] However, the size uniformity and performance uniformity of devices formed by these methods still need to be improved

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