Convolution operation device for improving data utilization rate

Abstract

The invention discloses a convolution operation device for improving a data utilization rate, which is characterized in that a multiply-accumulate unit adopts a parallel structure, input feature map data is split into a plurality of data blocks according to the parallelism degree of the multiply-accumulate unit, convolution operation is performed by taking the data blocks as units, and the same data block is repeatedly read and used; the convolution operation is completed with all the weights of the current network layer, the number of times of repeatedly inputting the data block into the cache is reduced, so that the data utilization rate is improved, the on-chip storage capacity requirement is reduced, the process of reading feature map data from off-chip storage is avoided, and the overall efficiency of convolution operation is remarkably improved.

Description

technical field [0001] The application belongs to the field of computers, and in particular relates to a convolution operation device for improving data utilization. Background technique [0002] In recent years, deep neural network technology has been widely used, especially in image processing, speech recognition and text classification applications. The deep neural network has excellent accuracy, and obtains more accurate results by analyzing huge data. The deeper the deep neural network, the stronger the simulation ability, and the higher the accuracy of reasoning. [0003] Convolutional neural networks are deep neural networks. Although the convolutional neural network has high accuracy, at the same time, as the number of neural network layers increases, the calculation amount of the convolutional neural network algorithm also becomes larger, and the requirements for data bandwidth and data storage are also higher. Since the resources implemented by the hardware are ...

AI Technical Summary

Problems solved by technology

Although the convolutional neural network has high accuracy, at the same time, as the number of neural network layers increases, the calculation amount of the convolutional neural network algorithm also becomes larger, and the requirements for data bandwidth and data storage are also higher.

Since the resources implemented by the hardware are limited, it cannot be realized that the algorithm increases with the increase of calculation amount.

Moreover, in the calculation process of the convolutional neural network, there is a feature that the convolution kernel window needs to slide over the entire image, resulting in a large amount of data being reused in the convolution operation.

However, the on-chip storage space of the computing device is limited, and the data needs to be temporarily stored in the external storage space, which leads to the limitation of the computing bandwidth and affects the computing efficiency.

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