Method of fabricating semiconductor device

Abstract

Disclosed herein are a method of fabricating a semiconductor device, and more particularly, a semiconductor device having different gate structures configured to provide an ultra-low critical voltage and a method of fabricating the same. The method comprises the following steps of respectively forming a channel region of a first nanostructure and a channel region of a second nanostructure in a first nanostructure layer and a second nanostructure layer; and forming a first all-around gate structure and a second all-around gate structure to respectively surround the channel region of the first nanostructure and the channel region of the second nanostructure. The step of forming the first all-around gate structure and the second all-around gate structure comprises the following sub-steps of selectively forming an n-type work function metal layer mainly comprising aluminum and a cover layer mainly comprising silicon on a channel region of the first nano-structure; depositing a plurality of double-layer aluminum-free p-type work function metal layers on the channel region of the first nanostructure and the channel region of the second nanostructure; depositing a fluorine barrier layer on the double-layer aluminum-free p-type work function metal layer; and depositing a gate metal filling layer on the fluorine barrier layer.

Description

technical field [0001] Embodiments of the present invention relate to the structure of field effect transistors (such as fin field effect transistors or fully wound gate field effect transistors), which have different gate structure configurations to provide ultra-low threshold voltages. Background technique [0002] As semiconductor technology progresses, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost increases. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as MOSFETs, including planar MOSFETs and FinFETs. Dimensional scaling increases the complexity of semiconductor processes. Contents of the invention [0003] In some embodiments, the method for manufacturing a semiconductor device includes forming a first stack and a second stack of a plurality of first nanostructure layers and a plurality of second nanostructure layers in a staggered arrangement on a...

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Problems solved by technology

Dimension shrinking increases semiconductor process complexity

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