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Debounce circuit with noise immunity and glitch event tracking

A debounce, circuit technology, applied in electrical components, pulse processing, pulse technology, etc., can solve problems such as introducing errors, destroying signals, and introducing errors in signals

Pending Publication Date: 2021-04-20
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Noise can corrupt the signal (possibly an asynchronous control signal) and introduce errors into the signal
Noise can intermittently introduce errors into the signal

Method used

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  • Debounce circuit with noise immunity and glitch event tracking
  • Debounce circuit with noise immunity and glitch event tracking
  • Debounce circuit with noise immunity and glitch event tracking

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] figure 1 A schematic diagram of the debounce circuit 100 is shown. The debounce circuit 100 includes a reset synchronizer circuit 101 and a logic circuit 106 . The reset synchronizer circuit 101 includes a first reset synchronizer 102 and a second reset synchronizer 104 . The first reset synchronizer 102 includes a first latch 108 and a second latch 110 . Each of the first latch 108 and the second latch 110 may be a set-reset (SR) flip-flop or a delay (D) flip-flop or the like. The second reset synchronizer 104 includes a third latch 112 and a fourth latch 114 , each of which can be an SR flip-flop or a D flip-flop or the like.

[0014] Logic circuit 106 includes AND gate 116 , OR gate 118 , buffer 119 , multiplexer 120 and output latch 122 . AND gate 116 may be any type of logic and digital device, and OR gate 118 may be any type of logic or digital device. Buffer 119 may be any type of delay element operable to delay signal transmission. The multiplexer 120 may ...

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PUM

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Abstract

A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

Description

technical field [0001] This application is directed to debounce circuits that mitigate and mask glitches. Background technique [0002] In microcontroller and system-on-chip (SoC) applications, among other applications, traces and wires, and the signals passing through them, are susceptible to external and environmental electrical noise. Noise can corrupt the signal (possibly an asynchronous control signal) and introduce errors into the signal. Noise can intermittently introduce errors into the signal. [0003] In electronic equipment, glitches may occur whereby an electronic signal changes its level due to noise or interference. For example, a signal of a logic 1 (active, asserted, or high) may temporarily become a logic 0 (deactivated, deasserted, or low). Contents of the invention [0004] This article provides debounce circuits for filtering, masking or mitigating glitches in electronic signals. A debounce circuit receives a signal and outputs an output signal with...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/1254
Inventor A·巴尔V·切拉尼
Owner STMICROELECTRONICS SRL