DMA automatic configuration module and system-on-chip SOC

Abstract

The invention provides a DMA automatic configuration module and a system-on-chip SOC, the DMA automatic configuration module is used for configuring a DMA controller through a bus, and the DMA automatic configuration module comprises: a slave bus interface module used for passively receiving a bus request; the main bus interface module that is used for actively initiating bus operation; the configuration information storage module that is used for storing configuration information of the DMA automatic configuration module; and the state machine control module that is used for controlling and executing the DMA configuration process. The DMA automatic configuration module can replace a CPU to execute a DMA configuration process, so that the CPU hardly needs to participate in the DMA configuration process, the load of the CPU is greatly reduced, hardware circuit implementation is not influenced by factors such as interruption, and the configuration efficiency is the highest.

Description

technical field [0001] The invention relates to the field of chip technology, in particular to a DMA automatic configuration module and a system on chip SOC. Background technique [0002] Driven by the new infrastructure and the background of Xinchuang, the encryption industry has ushered in new development opportunities, but also faces new challenges. In addition to the strong demand for high-performance encryption chips due to the increase in data traffic bandwidth of traditional security facilities, in many application scenarios, PCIe encryption Cards have become the most common form of equipment, and data transmission through PCIe to interact with the host has become one of the bottlenecks in the implementation of high-performance cryptographic chips. [0003] In the prior art, there are two mainstream solutions: 1. Use the SOC on-chip CPU to configure DMA to move data from the host storage medium to the chip encryption core, or from the chip encryption core to the host ...

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Problems solved by technology

However, both of these have their own difficulties and bottlenecks. In the first solution, the CPU is required to configure the DMA. After the DMA transfer is completed, an interrupt will be sent to the CPU. In addition, the chip calculation core is usually a multi-core design, so multiple data needs to be configured. Handling tasks and interrupts after processing are completed, which cause a large burden on the CPU, resulting in the inability to process other tasks; at the same time, the overall handling efficiency of the chip is still relatively low

In the second solution, multiple computing cores directly access the host storage medium through the PCIe interface. The scheduling module is quite complicated, and due to the delay effect of the data access of the computing cores, it is easier to form data congestion.

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