Offset value determination in a check node processing unit for message-passing decoding of non-binary codes

A technology of processing unit and check node, applied in error detection coding using multi-bit parity bits, coding elements, error correction/detection using block codes, etc., can solve problems such as unavailability, and achieve optimal decoding performance effect

Pending Publication Date: 2021-06-01
UNIVERSITY OF SOUTHERN BRITTANY
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, EMS algorithms still require substantial computational and storage resources, which may not be available in actual devices or systems, e.g. used in real-time applications or systems that require high throughput and significantly reduced latency

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  • Offset value determination in a check node processing unit for message-passing decoding of non-binary codes
  • Offset value determination in a check node processing unit for message-passing decoding of non-binary codes
  • Offset value determination in a check node processing unit for message-passing decoding of non-binary codes

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Embodiment Construction

[0038] Embodiments of the present invention provide devices and methods for determining offset values ​​and check node messages at a basic check node processing unit implemented in a check node processing unit of a non-binary error-correcting code decoder, the A non-binary error-correcting code decoder is used to decode a signal encoded using a non-binary error-correcting code.

[0039] Non-binary error correcting code decoders implementing devices and methods according to various embodiments may be implemented in several types of digital data transmission and storage devices and systems used in several types of applications. Exemplary devices and systems include, but are not limited to: computers, disks, laptops, phones, smartphones, recorders, base stations, drones, satellites, Internet of Things devices (IoT), embedded devices, and the like. Exemplary applications include magnetic and optical recording, digital television and video broadcasting, and digital communications. ...

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Abstract

Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit (300) also comprises a selection unit (303) which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit (300) then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (305).

Description

technical field [0001] The present invention relates generally to digital communications, and in particular to methods and apparatus for decoding signals encoded using non-binary error correcting codes. Background technique [0002] Error correcting codes are implemented in various data processing systems and devices to ensure protection of data from errors introduced during data transmission or storage in the presence of noise and / or interference. Encoding involves adding redundant data to original data that enables errors to be detected and / or corrected. [0003] Error correcting codes can be classified into two categories: linear codes and nonlinear codes. Linear error-correcting codes are particularly advantageous compared to non-linear codes because their implementation is less complex. Exemplary linear error correcting codes include convolutional codes and linear block codes, such as Hamming codes, Reed-Solomon codes, Turbo codes, polar codes, and low-density parity-...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/1111H03M13/112H03M13/114H03M13/1171H03M13/6583H03M13/6591H03M13/612
Inventor H·哈博E·布蒂永C·马尔尚
Owner UNIVERSITY OF SOUTHERN BRITTANY
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