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Accelerator and on-chip calculation module of accelerator

A computing module and accelerator technology, applied in the field of convolutional neural networks, can solve problems such as large data bandwidth requirements, high power consumption, and large storage resource occupation, and achieve the effects of reducing running time, power consumption, and storage resources.

Active Publication Date: 2021-06-18
上海西井科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it still has the disadvantages of large data bandwidth requirements, large storage resource occupation, and high power consumption.

Method used

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  • Accelerator and on-chip calculation module of accelerator
  • Accelerator and on-chip calculation module of accelerator
  • Accelerator and on-chip calculation module of accelerator

Examples

Experimental program
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Embodiment Construction

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0039] Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities ...

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Abstract

The invention provides an accelerator and an on-chip calculation module of the accelerator. The on-chip calculation module of the accelerator comprises a parameter distribution module which is configured to distribute calculation parameters, a data distribution module, amultiplication and addition module and multiple selectors, wherein the data distribution module is configured to distribute calculation data; the multiplication and addition module comprises a first summator, a first multiplier, a second summator and a second multiplier which are connected in sequence, and the first summator is connected to the data distribution module; each selector comprises a first input end, a second input end and an output end, the first input end is connected to the data distribution module, the second input end is connected to the parameter distribution module, and the output end of each selector is connected to the first summator, the first multiplier, the second summator and the second multiplier; and the first summator, the first multiplier, the second summator, the second multiplier, and the selector are configured to cause the accelerator on-chip computing module to perform different computing functions. According to the method, the data bandwidth requirement is reduced in the convolutional neural network calculation, the computing efficiency is improved, and the power consumption is reduced.

Description

technical field [0001] The invention relates to the field of convolutional neural networks, in particular to an accelerator and an on-chip computing module of the accelerator. Background technique [0002] Convolutional Neural Network (CNN) is a feedforward neural network. Its artificial neurons can respond to surrounding units within a part of the coverage area, and it has excellent performance for large-scale image processing. It mainly includes convolutional layer and pooling layer. Convolutional neural networks have been widely used in image classification, object recognition, and object tracking. [0003] Convolutional neural network computing can be implemented based on hardware such as FPGA (Field-Programmable Gate Array, that is, Field Programmable Gate Array), chips, etc. [0004] In the calculation of convolutional neural network, it can be divided into two categories. One is tensor convolution operation, which is characterized by multiplication and accumulation ...

Claims

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Application Information

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IPC IPC(8): G06F17/15G06F7/501G06F7/523G06N3/04G06F15/78
CPCG06F17/15G06F7/501G06F7/523G06F15/7807G06N3/048Y02D10/00
Inventor 谭黎敏吕斌宋捷
Owner 上海西井科技股份有限公司