Lightweight neural network hardware accelerator based on depth separable convolution

Abstract

The invention discloses a lightweight neural network hardware accelerator based on depth separable convolution. The lightweight neural network hardware accelerator comprises an A-path K * K channel convolution processing unit parallel array, an A-path 1 * 1 point convolution processing unit parallel array and an on-chip memory used for buffering a convolutional neural network and an input and output feature map, The convolutional neural network is a lightweight neural network obtained by compressing a neural network MobileNet by using a quantitative perception training method; The A-path K * K channel convolution processing unit parallel array and the multi-path 1 * 1 point convolution processing unit parallel array are deployed in a pixel-level assembly line; Each K * K channel convolution processing unit comprises a multiplier, a summator and an activation function calculation unit; and each 1 * 1 point convolution processing unit comprises a multiplexer, a two-stage adder tree and an accumulator. According to the invention, the problem of high-energy-consumption off-chip memory access generated in the reasoning process of the accelerator in the prior art is solved, resources are saved, and the processing performance is improved.

Description

technical field [0001] The invention belongs to the technical field of neural network hardware accelerators, and in particular relates to a lightweight neural network hardware accelerator based on depth-separable convolution. Background technique [0002] Today, convolutional neural networks have achieved great success in the fields of image classification, medical image segmentation, and object tracking. Typical convolutional neural networks (such as VGG16 and GoogLeNet) are computationally intensive and rely on high-cost, energy-inefficient graphics processing units or remote computing centers. It is difficult to deploy them on portable or mobile real-time systems under tight energy and cost budgets. Previous research has focused on two directions to solve this problem. One is to optimize the convolutional neural network at the algorithm level to reduce computation and storage access (such as topology optimization and model compression). Another direction is to design VL...

AI Technical Summary

Problems solved by technology

Existing convolutional neural network hardware accelerators such as Eyeriss and Google TPU are suitable for most known neural network models and have strong versatility, but for network models with irregular topologies such as those based on depthwise separable convolution Networks with low utilization of systolic arrays, which lead to unnecessary costs and energy losses

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