Digital multi-beam signal processing system and time synchronization method

Abstract

The invention discloses a time synchronization method for a digital multi-beam signal processing system. The method comprises the steps that: homologous 1PPS signals are obtained, and the 1PPS signals are made to act on a master control FPGA 0; first interrupt signals and second interrupt signals are generated; a first frame number of the master control FPGA 0 is configured, a second frame number of the master control FPGA 0 is read back, whether the first frame number is consistent with the second frame number or not is judged, and if the first frame number is consistent with the second frame number,the first frame number and the second frame number are matched as a synchronous frame number; the synchronous frame number is configured to a sub-FPGA, so that a first sub-synchronous frame number is obtained,and whether the first sub-synchronous frame number is consistent with a synchronous frame number wireless frame terminal is judged; the synchronous frame number is configured for a sub-FPGA through SPI total broadcast, so that a second sub-synchronous frame number of the sub-FPGA is obtained; and the second sub-synchronous frame number of the sub-FPGA is read back in a backboard polling mode, the second sub-synchronous frame number is compared with the synchronous frame number, and if the second sub-synchronous frame number is consistent with the synchronous frame number, system time synchronization succeeds. With the digital multi-beam signal processing system and the time synchronization method adopted,the time of the digital multi-beam signal processing system and the signal frames on an FPGA board are synchronized, and the information frames among the sub-FPGAs are reduced, so that frame loss and errors are avoided.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a digital multi-beam signal processing system and a time synchronization method. Background technique [0002] When processing digital signals in a large-scale phased array multi-beam system, multiple FPGA resources are often required to work together to complete large-capacity signal and data processing, but the timing of signals and frame numbers between each FPGA board is synchronized during digital signal processing etc. directly affect the performance of the system. The previous multi-beam signal processing system often used a high-precision clock as a time reference, and at the same time provided a time reference for each board. This puts forward higher requirements for the accuracy of the 10M clock, and for each FPGA Frame synchronization also cannot be used for further guidance and reference. Contents of the invention [0003] The purpose of the present inventio...

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Problems solved by technology

[0002] When processing digital signals in a large-scale phased array multi-beam system, multiple FPGA resources are often required to work together to complete large-capacity signal and data processing, but the timing of signals and frame numbers between FPGA boards is synchronized during digital signal processing etc. directly affect the performance of the system. The previous multi-beam signal processing system often used a high-precision clock as a time reference, and at the same time provided a time reference for each board. This puts forward higher requirements for the accuracy of the 10M clock. Frame synchronization is also unable to provide further guidance and reference

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