A Voltage Dump Circuit Applied to Multi-cell Battery Voltage Sampling
A voltage sampling and dumping circuit technology, applied in battery circuit devices, multiple synchronous battery arrangements, charge equalization circuits, etc., can solve problems such as unfavorable circuit integration, complex circuit structure, narrow input voltage range, etc., to improve single The effect of chip integration, increased compatibility, and improved common-mode voltage range
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[0019] figure 1 It is a schematic diagram of a voltage dump circuit, including a voltage dump sampling control circuit and a voltage dump switch circuit. When the input voltage VI+ and VI- are applied to the circuit and stabilized, if VI+ is greater than VI-, the voltage at point A V A Due to the clamping of PMOS transistor P4, the gate-source voltage is higher than VI-, if VI+ is less than VI-, V A It is a gate-source voltage higher than VI+. Assuming that VI is the minimum value of VI+ and VI-, the gate-source voltage of PMOS transistor P4 is V GSP4 , then there are:
[0020] V A =VI+V GSP4
[0021] In steady state, V A A gate-source voltage is lowered through the NMOS transistor N4 to obtain V B , depending on the clamping mechanism of the diode, V B A diode turn-on voltage drop V is reduced by Zener diode D1 D , thus obtaining the dump control voltage V C , assuming that the gate-source voltage of NMOS transistor N4 is V GSN4 , then there are:
[0022] V C =V...
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