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Configuration circuit for local dynamic reconstruction of password logic array

A dynamic reconstruction, cryptographic logic technology, applied in static memory, information storage, digital memory information and other directions, can solve the problems affecting computing performance, affecting reconstruction function, large amount of configuration information data, etc., to reduce waste, improve circuit performance effect

Active Publication Date: 2021-07-16
PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Configuration information is the basis for the realization of array functions. The amount of configuration information data required to complete the password calculation task is relatively large, which may easily lead to an excessive proportion of configuration storage resources in the overall structure, and reducing configuration storage resources may easily cause configuration information storage. Insufficient space will affect the realization of the reconstruction function and increase the delay of dynamic reconstruction, thus affecting the final computing performance

Method used

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  • Configuration circuit for local dynamic reconstruction of password logic array
  • Configuration circuit for local dynamic reconstruction of password logic array
  • Configuration circuit for local dynamic reconstruction of password logic array

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Embodiment Construction

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0038] In terms of configuration circuit design of cryptographic logic arrays, relevant research has been carried out mainly around the structure of reconfigurable cryptographic processors, and there are relatively few references on configuration circuits, and there are not many typical research results.

[0039] For reconfigurable computing processors, such as Figure 1a-Figure 1c As shown, the design of the configuration circuit mainly includes three typical...

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Abstract

The invention provides a configuration circuit oriented to local dynamic reconstruction of a password logic array. The configuration circuit comprises a register file, a configuration analysis circuit and a reconfigurable calculation unit, the register file is used for collecting and storing configuration information, extracting the configuration information based on the collected reconfigurable unit enable signal, and sending the configuration information to the configuration analysis circuit; the configuration analysis circuit is used for analyzing the configuration information output by the register file to obtain a configuration signal and sending the configuration signal to the reconfigurable calculation unit; the reconfigurable calculation unit is configured to respond to the configuration signal. All the configuration information to be reconstructed is pre-stored through the register file, so that the configuration information is prevented from being called from the outside of the array in each clock period, the replacement frequency of the configuration information is reduced, the dynamic power consumption is reduced, the waste of system calculation resources is reduced, and the circuit performance of the configuration circuit is improved.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a configuration circuit for local dynamic reconfiguration of a cryptographic logic array. Background technique [0002] Cryptographic Logic Array: It is a data flow-driven cryptographic processing structure and a typical application of reconfigurable computing technology in the cryptographic field. The interior of the array is regularly arranged with arithmetic units specially designed for cryptographic processing, supplemented by corresponding control logic and interconnection structure, and a specific data path is formed by configuring information to complete specific cryptographic computing tasks. [0003] Partial dynamic reconfiguration: refers to the process of reorganizing the circuit structure of the array part without affecting the overall calculation state during the array operation process, and changing its own circuit structure according to different applic...

Claims

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Application Information

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IPC IPC(8): G11C11/413
CPCG11C11/413Y02D10/00
Inventor 李伟高嘉浩章宇雷杜怡然陈韬南龙梅徐劲松金羽
Owner PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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