Clock gating circuit and method of operating the same

Abstract

A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal. The embodiment of the invention also relates to a method for operating the clock gating circuit.

Description

technical field [0001] Embodiments of the invention relate to clock gating circuits and methods of operation thereof. Background technique [0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as clock trees, are used to distribute a common clock signal to various circuits in order to synchronize the operation of the various circuits. In some cases, differences in the arrival time of a clock signal in two or more different circuits within an IC can cause errors that affect the performance of the IC. Additionally, as ICs become smaller and more complex, clock tree power consumption impacts IC performance and area. Contents of the invention [0003] According to an aspect of an embodiment of the present invention, there is provided a clock gating circuit, including: a NOR logic gate coupled to a first node, and configured to receive a first e...

AI Technical Summary

Problems solved by technology

In some cases, the difference in the arrival time of the clock signal in two or more different circuits within the IC can cause errors that affect the performance of the IC

In addition, as ICs become smaller and more complex, the power consumption of the clock tree also affects the performance and area of ​​the IC

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