System for updating chip software and hardware configuration in chip EDA simulation and application

Abstract

The invention discloses a system for updating chip software and hardware configuration in chip EDA simulation and application, and relates to the technical field of chip development. The system comprises: a GIT code library used for storing codes; the verifier client that is used for uploading a simulation code designed based on a hardware programming language to the GIT code library; the software personnel client that is used for uploading the C code to the GIT code library; the automatic conversion device that is used for acquiring the updated code and converting the updated code into a configuration information file with a configuration general format to store corresponding chip register configuration parameter information when the GIT code library is judged to have code updating; and when the verification personnel client or the software personnel client sends a code downloading request, converting the latest configuration information file into a simulation code or a C code designed based on a hardware language, and then sending the simulation code or the C code to the corresponding client. The system provided by the invention has few nodes, and the conversion efficiency and the conversion reliability of chip software and hardware configuration are improved.

Description

technical field [0001] The invention relates to the technical field of chip development, in particular to a system and application for updating chip software and hardware configurations in chip EDA simulation. Background technique [0002] With the increase of the design chip scale, chip verification (Verification) work becomes more and more important. The verification work runs through the entire chip design process, from behavioral HDL design to chip tape-out, a large number of EDA (Eletronic Design Automation, electronic design automation) verifications are required. Among them, the test case (case test) is to write a series of codes to verify the function or performance of the test item. Taking UVM (Universal Verification Methodology) verification commonly used in chip design as an example, the test case (casetest ) is based on the system verilog language, which generates incentives by using UVM sequence (UVM sequence). [0003] After obtaining the simulation results t...

AI Technical Summary

Problems solved by technology

In the above process, the configuration information needs to be transferred from the chip verification engineer to the software design engineer, and then back from the software design engineer to the chip verification engineer, and language conversion is required. On the one hand, the transfer of configuration information takes a lot of time iterations, on the other hand Because too many nodes will undoubtedly increase the probability of error

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