Multi-chip packaging structure and packaging method

Abstract

The invention provides a multi-chip packaging structure and packaging method. The packaging structure comprises a substrate, a first chip, a second chip and a plastic packaging layer, wherein the first chip and the second chip are sequentially stacked on the substrate, the plastic packaging layer wraps the first chip and the second chip, and the first chip and the second chip are electrically connected with the substrate; the substrate comprises a wiring area located on the periphery of the substrate and a non-wiring area located in the middle of the substrate, the non-wiring area is provided with a groove, and the first chip is arranged in the groove. The first chip is accommodated in the groove arranged in the non-wiring area of the substrate, so that the size of the whole packaging structure can be effectively reduced. Besides, when the first chip is fixed in the groove through a bonding layer (generally adopting glue such as chip mounting glue and the like), the arranged groove can well control overflow of the chip mounting glue, so that when the first chip is electrically connected with the substrate in a lead bonding mode, the risk that a bonding lead cannot be hit can be effectively reduced, and meanwhile, the relative height of the bonding wire arc can be effectively reduced, and the cost is saved.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and in particular relates to a multi-chip packaging structure and packaging method. Background technique [0002] Multi-chip packaging and device miniaturization are the future development direction of semiconductor devices. Multi-chip packaging technology is a packaging process that can meet the requirements of integration density and improve the performance of the whole machine. Generally, it can be divided into 2D structural packaging and 3D structural packaging, each of which has its own advantages and disadvantages. In order to cater to the development trend of miniaturization and functionalization of electronic products, it is often necessary to integrate more than two chips, even passive components such as capacitors, resistors, and inductors, into a package structure with a limited area. [0003] At present, the common 3D structure stacking combination packaging scheme is that a ...

AI Technical Summary

Problems solved by technology

This combined structure has the following disadvantages: (1) The front-loading chip is fixed on the substrate by the mounting adhesive, and since the mounting adhesive will overflow, it is necessary to control the distance between the bonding wire and the chip, the passive components and the conductive bumps. The block will be moved out correspondingly, which increases the plane size of the package structure; (2) Based on the limitation of the current flip-chip welding process, there is a risk of touching the bonding wire of the front-mounted chip when the flip-chip is mounted. The height of the bump and the process capability of the flip chip welding process require more input costs; (3) When the area between the flip chip and the front chip is filled with mold flow, there is a risk of insufficient space (height). , affecting product reliability

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