High-density static random access memory bit unit structure and process method thereof

Abstract

The invention discloses a high-density static random access memory bit unit structure and a process method thereof, which can improve the high-density performance of a bit unit and reduce power consumption and cost. The high-density static random access memory bit unit structure comprises a substrate, fins distributed on the surface of the substrate, gate regions distributed on the fins, a photoresist layer, a contact layer and a read bit line, wherein the bit unit comprises a fin-shaped field effect transistor, the length of each gate region is 22 nm, four fins are sequentially distributed at intervals in parallel, the fin distance between every two adjacent fins is FP, the contact layer distance is CPP, the vertical total width of an active region of the bit unit is 8*FP, the transverse total width of the active region is 2*CPP, and the minimum area of the active region of the bit unit is 0.0739 mu m<2>. The process method comprises the steps that: a self-alignment double pattern transfer process is adopted, the bit unit which comprises the four fins is obtained, the fin distance between every two adjacent fins is FP, the bit unit needs two photoresist layers, and the four fins are obtained through a photoetching process.

Description

technical field [0001] The invention relates to the technical field of field effect transistors, in particular to a high-density static random access memory bit unit structure and a process method thereof. Background technique [0002] Static random access memory (SRAM) is a memory device used for random access to data. "Static" means that the memory can keep the stored data constant when it is powered on. Static random access memory contains bit units, which are usually used as caches for CPU / GPU calculations. At present, SRAM bit units in highly integrated circuit chips account for about 30% to 60% of the entire chip area, of which The 6T high-density static random access memory (6T HD SRAM) containing six transistors is used more frequently. The main technical indicators of 6T HD SRAM include power consumption, unit area (for identifying density characteristics), process, and unit cost. Through the above indicators, each process technology node of 6T HD SRAM can be measu...

AI Technical Summary

Problems solved by technology

[0004] Aiming at the problems of unreasonable structure of SRAM bit cells in the prior art, resulting in poor high-density characteristics, high power consumption and high cost, the present invention provides a high-density SRAM bit cell structure and its process method , its structural design is simple and reasonable, which can improve the high-density characteristics of the bit cell, and at the same time reduce power consumption and cost

Images