TP chip power-on starting method for reducing SRAM space

Abstract

A TP chip power-on starting method for reducing an SRAM space comprises the following steps that S1, defining a register bit REMAP so as to carry out address mapping control through the bit, wherein the REMAP is equal to 0 when power-on is just started; s2, resetting the CPU by the IC internal module, stopping the operation of the CPU, carrying the Boot program stored in the Eflash into the Dramb through the Eflash Ctrl module, and releasing the CPU to reset after the carrying is completed; s3, starting to run Boot by the CPU, wherein the running space at the moment is Dramb, and the data cache space of the CPU is Drama; s4, after the Boot function is completed, configuring a register to enable REMAP to be equal to 1; when the REMAP is equal to 1, resetting the CPU, wherein the CPU is made to run again, at the moment, the running space of the CPU is mapped to the Eflash, the Drama and the Dramb which are all used as data cache areas, and routing allocation access to the Drama or carrying out the Dramb according to address division of the IC. According to the invention, the purposes of reducing the SRAM area and reducing the power consumption are achieved.

Description

technical field [0001] The invention relates to the technical field of chips, in particular to a method for power-on starting of a TP chip with reduced SRAM space. Background technique [0002] In today's globalization, the development of electronic products is also changing with each passing day, and there are constantly emerging electronic products that are very creative and closely related to human life. As people's requirements for quality of life gradually increase, wearable products can detect health indicators such as heart rate and blood pressure, so the wearable market is a huge potential market. Both terminal manufacturers and touch display IC companies will be committed to the development of wearable market products. develop. [0003] TP IC is an essential part of smart wearable devices, and smart wearable devices have higher and higher requirements on the area and power consumption of TP IC. [0004] For small embedded applications, SOC chips generally use SRAM...

AI Technical Summary

Problems solved by technology

[0008] When using Eflash as the APP running space, the two Boot running methods of the traditional solution also have their own shortcomings

The first type requires an additional Rom as the Boot running space. At this time, the Boot area is an independent area that requires an additional Rom storage device, so the IC area is increased. In addition, because the Rom is used as the Boot running space, the Boot needs It must be added to the production process when the IC is produced, so it cannot be modified

Once an error is found during subsequent chip verification, the error must be re-taped to correct the error, and the cost of fault tolerance is too high

The second type of Boot also runs in the Eflash space. The main function of the Boot is to upgrade or download APP files to the Eflash space. Because there is only one Eflash interface, it is necessary to switch the Eflash interface access to satisfy CPU instruction fetching and data access at the same time, resulting in The speed drops, and TP IC has requirements for the reporting time of the first frame

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