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Mask layout and semiconductor structure

A mask and semiconductor technology, which is applied in the field of mask layout and semiconductor structure, can solve the problems of semiconductor structure bridging and disconnection, achieve good contact, improve electrical performance, and not easy to bridge or short circuit

Pending Publication Date: 2021-11-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] With the continuous improvement of the integration level of integrated circuits, integrated circuits are developing rapidly in the direction of sub-micron and deep sub-micron, and the line width of the pattern will become thinner and thinner. The original pattern of one-time exposure now needs to be realized through multiple exposures. Higher requirements are placed on the precision of the semiconductor process, and in a multi-layer structure, a slight deviation between the upper layer pattern and the lower layer pattern will lead to bridging or disconnection defects in the final semiconductor structure

Method used

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  • Mask layout and semiconductor structure
  • Mask layout and semiconductor structure
  • Mask layout and semiconductor structure

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Embodiment Construction

[0033] Currently formed devices still suffer from poor performance. The reasons for the poor performance of the semiconductor structure are analyzed in conjunction with a semiconductor structure.

[0034] refer to Figure 1 to Figure 3 , is a structural diagram corresponding to a semiconductor structure.

[0035]The semiconductor structure includes: a bottom interconnection structure, and the bottom interconnection structure includes: a substrate (not shown in the figure); a first sub-interconnection layer 1 located on the substrate, and the first sub-interconnection layer 1 has an extension direction; the second sub-interconnection layer 2 is located on the substrate on one side of the first sub-interconnection layer 1, and the second sub-interconnection layer 2 and the first sub-interconnection layer 1 are arranged at intervals, the second sub-interconnection layer 2 extends along the second direction, the extension direction of the second sub-interconnection layer 2 is per...

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Abstract

The invention discloses a mask layout and a semiconductor structure. The mask layout comprises a first mask layout which comprises a first sub-pattern, and a second sub-pattern and a third sub-pattern which are located at one side of the first sub-pattern, wherein the second sub-pattern and the third sub-pattern are located in the same layout, and the first sub-pattern extends in a first direction; the second sub-pattern extends in a second direction, the first direction is perpendicular to the second direction, and the extension direction of the second sub-interconnection layer intersects with an extension direction of the first sub-interconnection layer; and in the first direction, the third sub-pattern is located on at least one side of the second sub-pattern, and the third sub-pattern is connected with the end, close to one side of the first sub-pattern, of the second sub-pattern. According to the mask layout of the invention, in the exposure process, the formed second sub-interconnection layer is longer in the second direction, correspondingly, a formed contact plug is easy to form on the second sub-interconnection layer, the contact plug is in good contact with the second sub-interconnection layer, and the electrical performance of the semiconductor structure is improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a mask layout and a semiconductor structure. Background technique [0002] Before the photolithography process starts, the wafer layout will be copied onto the mask plate by specific equipment, and then the light of a specific wavelength (such as 248 nm ultraviolet light) will be generated by the photolithography equipment to convert the pattern on the mask plate Replicated onto the physical wafer used for production. [0003] Photolithography (Lithograph) is a key process technology for realizing integrated circuit patterns. In photolithography, the photosensitive material (photoresist) is coated on the base film, and the light of the wavelength band corresponding to the photosensitive characteristics of the photoresist is used to irradiate the surface of the photoresist through a mask with a specific pattern. After developing, a photoresist...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/00H01L23/528H01L23/522
CPCG03F1/00H01L23/528H01L23/5226
Inventor 杨青
Owner SEMICON MFG INT (SHANGHAI) CORP
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