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Semiconductor structure and forming method thereof

A semiconductor and graphics technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, and semiconductor/solid-state device components, etc., it can solve problems such as having a great impact on performance and affecting the normal operation of semiconductor devices, improving electrical performance and avoiding engraving. Over-etching or under-etching, resulting in good quality results

Pending Publication Date: 2021-10-22
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, compared with the miniaturization of components and the increase of integration, the number of conductor connections in the circuit continues to increase, and the formation quality of the interconnection structure has a great impact on the performance of the back-end (Back End Of Line, BEOL) circuit. Will affect the normal operation of semiconductor devices

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0030] Currently formed devices still suffer from poor performance. The reasons for the poor performance of the device are analyzed in conjunction with a method of forming a semiconductor structure.

[0031] refer to Figure 1 to Figure 5 , shows a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0032] Such as figure 1As shown, a substrate 1, an anti-etching material layer 2 on the substrate 1 and a pattern definition layer 3 on the anti-etch material layer 2 are provided; a mask layer 4 is formed on the pattern definition layer 3 .

[0033] Such as figure 2 As shown, using the mask layer 4 as an implantation mask, doping ions in the pattern definition layer 3 between the mask layers 4 to form a doped layer 5, the resistance of the doped layer 5 The etch degree is greater than the etch resistance of the pattern definition layer 3 .

[0034] Such as image 3 As shown, after the doped layer 5 is formed, the mas...

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PUM

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Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps: providing a substrate, an etching stop material layer located on the substrate, a first anti-etching material layer located on the etching stop material layer and a doping layer located on the first anti-etching material layer; etching the first anti-etching material layer by taking the doped layer as a mask to form a first anti-etching layer; and etching the etching stop material layer by taking the first anti-etching layer as a mask to form an etching stop structure. According to the embodiment of the invention, in the process of forming the first anti-etching layer, the top of the etching stop material layer is taken as the etching stop position, so that a bottom convex corner in the doping layer is not easy to transfer into the first anti-etching layer, and the forming quality of the first anti-etching layer is better; similarly, in the process of forming the etching stop structure, the top of the substrate is taken as an etching stop position, so that the influence of a bottom convex angle phenomenon on the etching stop structure is further reduced, and finally, the forming quality of the etching stop structure is better.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] As semiconductor manufacturing technology becomes more and more sophisticated, integrated circuits are also undergoing major changes. The number of components integrated on the same chip has increased from the initial dozens or hundreds to the current millions. In order to meet the requirements of circuit density, the manufacturing process of semiconductor integrated circuit chips uses batch processing technology to form various types of complex devices on the substrate and connect them to each other to have complete electronic functions. At present, most of them are used between wires. The ultra-low-k interlayer dielectric layer is used as the dielectric material to isolate each metal interconnection, and the interconnection structure is used to provide...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/528
CPCH01L21/76802H01L23/528H01L2221/101
Inventor 王士京何其暘何欣祥卑多慧杨明姚达林黄敬勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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