Adaptive PAM4 decision feedback equalization circuit

Abstract

The invention relates to an adaptive PAM4 decision feedback equalization circuit, which comprises a decision feedback equalization main circuit and an adaptive circuit, and is characterized in that the main circuit comprises an adder, a first decision device, a second decision device, a third decision device, a first delay unit group, a second delay unit group, a third delay unit group, a decoder and a DSP coefficient table; and the self-adaptive circuit comprises an eye pattern monitoring module and a self-adaptive module, wherein the self-adaptive module comprises a comparison unit, a delay unit and a coefficient regulation and control unit. According to the invention, the DSP technology replaces a multiplier and an adder in a decision feedback equalization feedback loop, the design of a front-end circuit ADC is omitted, the power consumption is effectively reduced, and the influence of ADC quantization noise on signals is avoided. Meanwhile, automatic updating of coefficients is achieved through eye pattern monitoring and a self-adaptive algorithm, and the application scene of decision feedback balance is widened.

Description

technical field [0001] The application relates to the technical field of chiplet high-speed interface chip design, in particular to an adaptive PAM4 decision feedback equalization circuit. Background technique [0002] As the rate of transmitting information continues to increase, bandwidth issues have become increasingly prominent. PAM4 (4-level Pulse Amplitude Modulation, four-level pulse amplitude modulation) signal replaces the traditional NRZ signal and becomes one of the effective methods to solve this problem. Moreover, the end of Moore's Law will increase the demand and use of SerDes chiplets to meet the chip power and performance requirements of applications such as high-performance computing processors, high-performance AI computing, and IoT / wireless edge. In the entire chiplet interface link, the equalization technology can effectively compensate the high-frequency attenuation signal caused by the chiplet interconnection channel, especially in the transmission ch...

AI Technical Summary

Problems solved by technology

The traditional PAM4 DFE has a simple structure, low circuit complexity, and low power consumption, but it can only perform 1-tap coefficient compensation, which will greatly deteriorate the transmission quality and bit error performance of the link, and is not suitable for transmission channel occasions with severe tailing , at the same time, the circuit structure does not have an adaptive function, nor can it automatically track and compensate for changes in channel characteristics, and the traditional circuit is subject to great application restrictions.

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