Automatic searching method for maximum operation frequency of cryptographic algorithm in FPGA (Field Programmable Gate Array)

Abstract

The invention provides an automatic searching method for the maximum operation frequency of a cryptographic algorithm in an FPGA. The method comprises the steps of obtaining an initial reference point on a Slack-Period curve in the cryptographic algorithm; judging the relative position of the initial reference point and the maximum operation frequency point, and searching for a new reference point; on the basis of the initial reference point and the new reference point, searching the maximum operation frequency point backwards in parallel through multiple processes; outputting the maximum operation frequency; static time sequence analysis and a unique heuristic algorithm are used for searching for the maximum operation frequency of the cryptographic algorithm, script driving and multi-process parallel execution are utilized, and the searching time is shortened.

Description

technical field [0001] The disclosure belongs to the technical field of cryptographic algorithm integrated circuits, and in particular relates to an automatic search method and system for a maximum operating frequency of a cryptographic algorithm in an FPGA. Background technique [0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art. [0003] In the digital information age, cryptographic algorithms have received more and more attention. Many companies are actively developing hardware that can implement lightweight cryptographic algorithms on mobile terminals, especially in combination with future Internet of Things applications. , the FPGA method is a major mainstream direction for the realization of hardware cryptographic algorithms today; FPGA is a field programmable logic gate array, which appears as a semi-custom circuit in the field of ASIC, which not only solves the sho...

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Problems solved by technology

[0006] (1) Xilinx's EDA tool Vivado will not report the maximum frequency that the corresponding code can achieve, the tool will only report "pass" or "fail" to achieve the goal; Altera's EDA tool Quartus Prime will report the maximum frequency, but it is not accurate , and when changing the target frequency, Quartus will return another maximum frequency, causing the maximum frequency reported by the tool to be inaccurate;

[0007] (2) For the problem of the maximum clock frequency supported by the hardware code, the traditional method is to manually try different target frequencies; in the process, the results obtained will vary from person to person, and this is a very boring and time-consuming the process of

[0008] (3) The slack-period curve of the cryptographic algorithm fluctuates frequently and irregularly, and the difficulty of searching for the maximum operating frequency of the cryptographic algorithm will undoubtedly increase the product design cycle of the FPGA; the complexity and diversity of the slack-period curve lead to the search The maximum operating frequency of the cryptographic algorithm has become a major difficulty, and the classic dichotomy method is not only tedious and time-consuming, but also usually cannot get the correct result; figure 1 Shown is the Slack-Period partial curve of the SILC_GMU_v1.0 cryptographic algorithm implemented on the 10CL016YU256C8G FPGA of Altera's Cyclone10LP. Using the traditional binary search method, the correct result cannot be found

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