Packaging structure and forming method thereof
A packaging structure and packaging substrate technology, which is applied to electrical components, electrical solid devices, circuits, etc., can solve the problem that the reliability of the packaging structure needs to be improved, and achieve the effects of avoiding breakage or peeling, improving reliability, and reducing pressure.
Pending Publication Date: 2021-11-12
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0004] However, the reliability of the packaging structure formed by the existing semiconductor devices needs to be improved
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Embodiment Construction
[0022] It can be seen from the background art that the reliability of the packaging structure formed by the existing semiconductor devices needs to be improved.
[0023] The inventors found that, in order to overcome the parasitic effect of the metal interconnection structure, an interlayer dielectric layer with an ultra-low dielectric constant (Ultra-low dielectric constant, ULK) is usually formed between the metal interconnection structures. When the layer encounters external stress, it is easy to cause fracture or peeling off. Especially when using a typical porous material with an ultra-low dielectric constant, since the interlayer dielectric layer is a porous material with an ultra-low dielectric constant (hereinafter referred to as ULK material), it is easy to Cause the ULK material to break or peel off, or, even when there is no external stress, due to the different expansion coefficients of different materials in the packaging structure, the temperature change in the e...
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The embodiment of the invention provides a packaging structure and a forming method thereof, and the packaging structure comprises a substrate which comprises an interlayer dielectric layer; a welding pad positioned on the surface of the substrate; a bump lower metal layer positioned on the welding pad; and a conductive bump on the the bump lower metal layer, wherein the projection of the extension line of the conductive bump on the substrate along the extension direction of the conductive bump passes through the central point of the surface of the substrate, so that the area of a stress-bearing region of the conductive bump is maximized, the pressure intensity of the region when the conductive bump is stressed is reduced, the interlayer dielectric layer in the substrate is prevented from being broken or stripped, the maximum stress which can be borne by the packaging structure is improved, and the reliability of the packaging structure is further improved.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a packaging structure and a forming method thereof. Background technique [0002] When forming a semiconductor device, the electrical connection between semiconductor devices needs to be realized through a metal interconnection structure. With the continuous improvement of semiconductor integrated circuit process technology, when semiconductor devices are reduced to a deep submicron range, the density of metal interconnection structures between semiconductor devices is also increasing. Parasitic resistance and parasitic capacitance are easily generated between high-density metal interconnection structures, resulting in parasitic effects, which lead to time delays in signal transmission between devices. [0003] In order to overcome the parasitic effect of the metal interconnection structures, an interlayer dielectric layer with ultra-low dielectric constant (Ultra-low ...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L23/485H01L21/60
CPCH01L23/4824H01L24/03H01L2224/03914H01L2224/0231H01L2224/02331H01L2224/02333H01L2224/02381H01L2224/0401
Inventor 熊鹏肖代兵王瑜彬李斌施维
Owner SEMICON MFG INT (SHANGHAI) CORP