Negative capacitance L-shaped gate tunneling field effect transistor and preparation method thereof

Abstract

The invention belongs to the technical field of microelectronic devices, and discloses a negative capacitance L-shaped gate tunneling field effect transistor and a preparation method thereof. The negative capacitance L-shaped gate tunneling field effect transistor comprises a buried oxide layer, a P-substrate, an N + type interlayer, a P + type source region, a gate oxide layer medium, a ferroelectric medium layer, a gate region and a drain region; the P + type source region and the N + type interlayer are located in the upper left portion of the P-substrate from top to bottom, the gate oxide layer medium is located in the right side of the N + type interlayer, the gate region is located on the gate oxide layer, the drain region is located on the right portion of the P-substrate, and the buried oxide layer is located below the P-substrate. A metal / / Hf0.5Zr0.5O / HfO2 / Si stacked structure is formed in the left side of the P + source region, so that the grid control capability is improved, the channel surface potential is increased, and the on-state current of the tunneling field effect transistor TFET is improved; and the N + interlayer and the P + source region are generated in the left side of the gate region, the tunneling area is increased, and line tunneling is expected to be formed.

Description

technical field [0001] The invention relates to the technical field of microelectronic devices, in particular to a negative capacitance L-type gate tunneling field effect transistor and a preparation method thereof, which can be used in the preparation of large open current and low power consumption electronic devices. Background technique [0002] In the process of continuous miniaturization of complementary MOS technology, adjusting the power supply voltage is the most effective way to reduce power consumption. However, taking this approach in nanoscale circuits will no longer be feasible. A low threshold voltage causes a drastic increase in device leakage current, further increasing the static power consumption of the device. As a breakthrough, tunneling field-effect transistor TFET with gate-controlled reverse-biased p-i-n diode structure has become one of the candidates for next-generation low-power devices due to its low leakage current and steep subthreshold slope. ...

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Problems solved by technology

[0003] However, limited by the innovation of the device structure and the diversity of heterogeneous materials, the improvement of device characteristics is limited, and the tunneling probability of the traditional L-channel tunneling field effect transistor LG-TFET is difficult to increase

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