Word line leading-out structure and preparation method thereof

Abstract

The invention relates to a word line leading-out structure and a preparation method thereof. A word line extending in the X-axis direction is formed on a substrate; a contact hole covering the word line in the Y-axis direction is formed, wherein the X-axis direction is perpendicular to the Y-axis direction; and a metal wire covering the contact hole is formed, wherein the contact hole is positioned between the word line and the metal wire and is contacted with the word line and the metal wire separately, and the contact area of the contact hole and the metal wire is larger than that of the contact hole and the word line. According to the word line leading-out structure, the contact area of the contact hole and the metal line is larger than the contact area of the contact hole and the word line, so that the contact resistance of the word line leading-out structure can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a preparation method of a word line lead-out structure and a bit word lead-out structure. Background technique [0002] Semiconductor memory uses transistor arrays to control the charge and discharge of storage capacitors to access data. Wherein, the gate of the transistor is electrically connected to the word line, and after the word line is formed in the substrate, a word line lead-out structure needs to be formed above the word line, and the word line is electrically connected to an external control circuit through the word line lead-out structure. [0003] However, with the continuous improvement of the integration level of semiconductor devices, the size of the word lines and the continuous reduction of the spacing between the word lines, the area of ​​the word line lead-out structure will also be correspondingly reduced, so that the distance between the word line lead-out stru...

AI Technical Summary

Problems solved by technology

[0003] However, with the continuous improvement of the integration level of semiconductor devices, the size of the word lines and the continuous reduction of the spacing between the word lines, the area of ​​the word line lead-out structure will also be correspondingly reduced, so that the distance between the word line lead-out structure and the corresponding word line The contact resistance becomes larger, causing the current flowing through the word line to be too small, thereby reducing the sensing margin of the semiconductor memory and the charging and discharging speed of the storage capacitor

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