Unlock instant, AI-driven research and patent intelligence for your innovation.

A chip verification system, method, device, electronic equipment and storage medium

A technology for verifying systems and chips, applied in electrical digital data processing, computer-aided design, instruments, etc., can solve problems such as unfavorable maintenance, errors, and inability to guarantee the correctness of instruction stream semantics, so as to simplify complexity, improve reliability and The effect of accuracy

Active Publication Date: 2022-02-11
上海燧原科技有限公司
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of implementing the present invention, the inventor found that the existing technology has the following defects: because the instruction sequence of the verification model cache needs to be disturbed and then executed, so that the verification model handles the out-of-order behavior, which increases the complexity of the verification model , and the verification logic is tightly coupled with the internal timing of RTL, which is not conducive to maintenance
At the same time, since the verification model and RTL are both executed out of order, the correctness of the instruction flow semantics cannot be guaranteed. It is easy to happen that the verification model and the RTL design are the same, but there are errors at the same time, resulting in the verification being passed even when there is a problem with the chip. It is difficult to guarantee the reliability and accuracy of the chip verification system

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A chip verification system, method, device, electronic equipment and storage medium
  • A chip verification system, method, device, electronic equipment and storage medium
  • A chip verification system, method, device, electronic equipment and storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] figure 1 It is a schematic structural diagram of a chip verification system provided in Embodiment 1 of the present invention, as shown in figure 1 As shown, the structure of the chip verification system includes: a verification model module 110, an out-of-order buffer module 120, a chip task execution module 130, and a result comparison module 140; 120 is communicatively connected with the result comparison module 140, and the chip task execution module 130 is communicatively connected with the result comparison module 140; wherein:

[0038] The verification model module 110 is used to output the positive sequence output results according to the verification stimulus, and sends the positive sequence output results to the out-of-order buffer module 120; the out-of-order buffer module 120 is used to perform out-of-order processing on the positive-order output results to obtain the first out-of-order output results in order, and send the first out-of-order output results...

Embodiment 2

[0050] Figure 4 It is a schematic structural diagram of a chip verification system provided by Embodiment 2 of the present invention. This embodiment is embodied on the basis of the above-mentioned embodiments. In this embodiment, the specific implementation of the verification model module and the out-of-order buffer module is given. The chosen implementation. Correspondingly, as Figure 4 As shown, the chip verification system includes: a verification model module 110, an out-of-order buffer module 120, a chip task execution module 130 and a result comparison module 140; wherein:

[0051] The verification model module 110 may include a functional logic unit 111 and an instruction recording unit 112; the functional logic unit 111 is communicatively connected with the instruction recording unit 112, wherein: the functional logic unit 111 is used to respond to the verification stimulus, generate a stimulus response result, and send the stimulus response result Send to the in...

Embodiment 3

[0072] Image 6 It is a flow chart of a chip verification method provided by Embodiment 3 of the present invention. This embodiment is applicable to chip verification. The method can be executed by a chip verification device, which can be implemented by software and / or hardware. implementation, and generally can be integrated in electronic equipment. Correspondingly, such as Image 6 As shown, the method includes the following operations:

[0073] S310. Obtain the first out-of-order output result output by the out-of-order buffer module; wherein, the out-of-order buffer module performs out-of-order processing on the positive-order output result output by the verification model module according to the verification stimulus. get.

[0074] S320. Obtain a second out-of-sequence output result output by the chip task execution module according to the verification stimulus.

[0075] S330. Perform chip verification according to the first out-of-sequence output result and the secon...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The embodiment of the present invention discloses a chip verification system, method, device, electronic equipment, and storage medium. The system includes a verification model module, an out-of-order buffer module, a chip task execution module, and a result comparison module; Output the positive sequence output results, and send the positive sequence output results to the out-of-order buffer module; the out-of-order buffer module is used to perform out-of-order processing on the positive-order output results, obtain the first out-of-order The result is sent to the result comparison module; the chip task execution module is used to output the second random output result according to the verification stimulus, and the second random output result is sent to the result comparison module; the result comparison module is used to output the result according to the first random order and the second out-of-sequence output result for chip verification. The technical solution of the embodiment of the present invention can simplify the complexity of the verification model, and at the same time improve the reliability and accuracy of the chip verification system.

Description

technical field [0001] The embodiments of the present invention relate to the field of chip technology, and in particular, to a chip verification system, method, device, electronic equipment, and storage medium. Background technique [0002] One of the purposes of chip verification is to detect whether there are bugs (vulnerabilities) in the program running on the chip, that is, to verify whether the function of the chip is normal. During chip verification, the chip verification system's RTL (Register Transfer level, register conversion level circuit) simulator and verification model execute verification stimulation and output execution results. The chip verification system compares the RTL output results with the verification model output execution results, Realize the verification of the chip. With the rise of artificial intelligence applications, the integration scale and design complexity of high-performance computing chips are increasing day by day, and the instruction...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/3308
CPCG06F30/3308
Inventor 叶楚楚陈梦远
Owner 上海燧原科技有限公司