Data transmission system of FPGA and DSP based on SRIO protocol

Abstract

The invention discloses a data transmission system between an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) based on an SRIO (Serial Radio Input / Output) protocol. A clock generation module generates M synchronous sampling clocks, and M channel binding modules are used for splicing and storing acquired data of acquisition board cards adopting the corresponding synchronous sampling clocks, a polling module is used for reading the spliced data from the corresponding channel binding module according to a reading signal of the DSP, a data unbinding module carries out data bit width expansion and data unbinding and then stores the spliced data into the asynchronous FIFO5, a transmission packet generation module reads the data from the asynchronous FIFO5, a transmission packet is generated according to the requirement of an SRIO protocol, and the SRIO transmission module sends the transmission packet to the DSP module for subsequent processing. According to the invention, data transmission with multiple synchronization systems, multiple channels and any bit width can be realized.

Description

technical field [0001] The invention belongs to the technical field of data transmission, and more specifically, relates to a data transmission system based on the FPGA and DSP of the SRIO protocol. Background technique [0002] With the development of integrated circuit technology, FPGA, CPU, DSP and other processors are constantly updated and iterated, and their performance has been greatly improved. High-speed data transmission between FPGA and these processors is very common and is often used in various high-speed data acquisition systems. With the development of technology, the data acquisition system tends to be more and more complex embedded system, and the high-speed transmission interface equipped with the necessary mainstream microprocessor is becoming more and more abundant and efficient. With the continuous improvement of FPGA performance, it has gradually become an indispensable part of the data acquisition system. A high-speed Serdes interface is often integra...

AI Technical Summary

Problems solved by technology

Synchronous sampling technology is a variable-rate sampling, and the sampling clock changes with the signal to be tested. Therefore, the stability of the synchronous sampling clock is usually difficult to guarantee, which in turn affects the accuracy of back-end data processing.

Images