Ferroelectric based transistors

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of manufacture. The ferroelectric based transistor includes: a semiconductor-on-insulator substrate including a semiconductor material, a buried insulator layer under the semiconductor material and a substrate material under the semiconductor channel material; a ferroelectric capacitor under the buried insulator layer and which includes a bottom electrode, a top electrode and a ferroelectric material between the bottom electrode and the top electrode; a gate stack over the semiconductor material; a first terminal contact connecting to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connecting to the top electrode of the ferroelectric capacitor.

Description

technical field [0001] The present disclosure relates to semiconductor structures, and more particularly, to ferroelectric-based transistors and methods of fabrication. Background technique [0002] Ferroelectric Field Effect Transistor (FeFET) gate stack structures are characterized by ferroelectric (FE) material integration, where a buffer interfacial layer is grown between the ferroelectric material layer and the Si substrate. The buffer interface layer has an intrinsically lower dielectric constant compared to the ferroelectric material, thereby altering the gate stack field distribution towards an increased field at the buffer interface layer and a decreased field across the ferroelectric material . Consequently, the FeFET operating range is shifted towards higher write conditions with severe charge injection and trapping in the ferroelectric material layer, resulting in limited endurance of the memory. Endurance and writing conditions are key challenges for FeFETs to...

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Problems solved by technology

This results in a reduced P r value, and thus limits the maximum achievable memory window for a certain ferroelectric material layer thickness increase

[0008] Furthermore, write / read disturb is challenging for FeFETs with integration into the array structure, which leads to considering special read / write schemes to avoid changing the memory state of unselected devices in the array

However, this will increase the complexity of array operations

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