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Peak current testing and correcting method and control circuit

A peak current and control circuit technology, which is applied in the direction of AC/pulse peak measurement, control/regulation system, and adjustment of electrical variables, etc., can solve the problems that the probe cannot carry too much current and exceed the current capacity of the probe, and realize the cost The effect of low, simple circuit structure

Active Publication Date: 2021-12-21
SUZHOU KAIWEITE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, the probe contact is used to control the circuit during the wafer CP test, and the probe cannot carry too much current. Usually, the maximum current that the probe can withstand is about 100mA~200mA, and the output peak current is generally Ampere ratings, well beyond the probe's current capability

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  • Peak current testing and correcting method and control circuit

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Embodiment

[0026] Example: such as figure 2 As shown in the figure, VIN and SW are the pins of the circuit, corresponding to the window-opening pads during the CP test of the wafer, T1, T2, and OUT are the ports for the CP test of the wafer; R1 and R2 are resistors; INV1 , INV2 is an inverter digital circuit; N1 and N2 are NMOS tubes, N1 is a high-current output power tube, N2 is a mirror current tube, and the channel lengths of N1 and N2 are the same and the channel width ratio is N: 1, that is, N1 and N2 The on-resistance ratio of N2 is 1:N; Comp is a comparator circuit, and its positive and negative input terminals are respectively connected to the source terminals of N1 and N2 to compare the source terminal voltages of N1 and N2; Iref is the current reference; LOGIC, The LOGIC1 circuit is a logic control circuit for controlling the opening and closing of N1 and N2.

[0027] 1. In normal working mode, T1 and T2 ports are suspended, because R1 and R2 pull down the input of INV1 and I...

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Abstract

The invention discloses a peak current testing and correcting method, which comprises the following steps: 1) setting a T1 port to be at a high level, setting a T2 port to be at a low level, and measuring the conduction impedance of a tube N1 between a VIN pin and an SW pin; 2) setting a T1 port to be at a low level, setting a T2 port to be at a high level, and enabling the NMOS tube N2 to be in a conducting state; (3) enabling a T2E port to set the VG1 to be at a low level all the time by controlling a LOGIC1 circuit, enabling a current reference Iref to generate voltage drop on conduction impedance of an NMOS transistor N2, observing the voltage of an OUT port, and calculating peak current; and 4) adjusting the size of the current reference through programming, and further adjusting the voltage drop generated by the current reference Iref on the conduction impedance of the tube N2. According to the invention, the problem that Ipk large current is directly tested during the CP test of the wafer is solved; the circuit is simple in structure, can be realized by adding a small number of control circuits on the basis of an original circuit, and is low in implementation cost.

Description

technical field [0001] The invention relates to the field of analog integrated circuit design, in particular to a peak current testing and correction method and a control circuit. Background technique [0002] The voltage conversion circuit is mainly divided into a current mode voltage conversion circuit and a voltage mode voltage conversion circuit. As a common voltage conversion circuit, the current mode voltage conversion circuit has the advantages of fast response speed, simple loop compensation and safe peak current control. . [0003] The peak current control circuit of the output power tube of the current mode voltage conversion circuit such as figure 1 As shown, the IN signal sets VG to high level through the LOGIC circuit, turns on the NMOS transistors N1 and N2, and the current reference Iref will generate a voltage drop VIN-Vref on the on-resistance of N2, and VIN is the input voltage of the voltage conversion circuit. The output current flows from the input vol...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R19/04G05F1/10
CPCG01R19/04G05F1/10
Inventor 张胜涂才根谭在超罗寅丁国华
Owner SUZHOU KAIWEITE SEMICON