Semiconductor device epitaxy process and semiconductor device comprising epitaxial layer formed thereby

Abstract

The invention relates to a semiconductor device epitaxy process, and relates to a manufacturing technology of a semiconductor integrated circuit. The process comprises the following steps: on a semiconductor substrate on which a plurality of dummy gate structures are formed, forming grooves in two sides of the dummy gate structures in a self-alignment manner through an etching process; forming an initial seed crystal layer on the surface of the inner side of the groove through an epitaxial process, wherein the initial seed crystal layer located at the bottoms of the grooves is thicker, and the initial seed crystal layer located on the side walls is thinner; longitudinally etching the initial seed crystal layer to thin the bottom of the initial seed crystal layer so as to form a seed crystal layer; forming a main body layer on the seed crystal layer through an epitaxial process, wherein the main body layer fills the grooves; and forming a buried covering layer on the main body layer through the epitaxial process, so that the thickness of the main body layer can be increased as much as possible on the basis of effectively isolating carrier conduction of the main body layer and a channel in a static state and reducing leakage current, the channel stress is enhanced, and the electrical performance of the device is improved.

Description

Technical field [0001] The present invention relates to a semiconductor integrated circuit manufacturing technique, and more particularly to a source leakage region of a semiconductor device. Background technique [0002] With the development of semiconductor technology, the key size (CD) of the device is getting smaller and smaller. When the process node of the device reaches 28 nm or less, it is often necessary to use an embedded epitaxial layer to change the stress of the channel area in the source leak area to improve the stress of the channel area. The mobility of the stream is thereby increasing the performance of the device. [0003] See Figures 1A to 1D , Figures 1A to 1D A sectional view of the device in the process of the prior art embedded epitaxial layer, such as Figure 1A As shown, after the pseudo gate structure 120 of the device, the groove 110 is formed from both sides of the dummy gate structure 120 of the semiconductor substrate 100, and the groove is usually a ...

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Problems solved by technology

[0007] However Figure 1b As shown, when forming the seed layer 111 close to the wall of the groove 110, due to the difference in growth rate between the and crystal planes, the thickness of the seed layer 111 at the bottom of the groove 110 is very thick, while the side very thin walls

This is not conducive to the sidewall blocking the diffusion of carriers, but also reduces the volume of the main body layer 112, which causes a reduction in stress, thereby reducing the performance of the device.

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