Power type chip packaging method

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly discloses a power type chip packaging method. The method comprises the following steps of configuring a packaging bottom plate; configuring a protective shell; and enabling the packaging bottom plate and the protective shell to be thermally connected and formed, wherein the step of configuring the packaging bottom plate comprises the steps that a geometric center is determined on a substrate, the geometric center divides the substrate into four areas through two perpendicular axes, one area is a low-heat-production element area, and the two areas close to the low-heat-production element area are a high-heat-production and high-heat-resistance element area and a high-heat-production and low-heat-resistance element area respectively; the step of configuring the protective shell comprises the following steps: forming a relatively thin concentrated outer conduction area in the middle of the protective shell, enabling a straight conduction area to extend to the concentrated outer conduction area from the high-heat-production and high-heat-resistance element area; a circular ring-shaped annular guide area with relatively thin thickness is formed around the high-heat-production and low-heat-resistance element area; and before the packaging bottom plate and the protective shell are thermally connected and formed, a power type chip is fixed on the substrate, and the packaging bottom plate and the protective shell are thermally connected and formed. The structure of the packaging shell is reserved to ensure the packaging safety of the power type chip, and a good heat dissipation effect is achieved.

Description

technical field [0001] The present application relates to semiconductor packaging, in particular to a method for packaging power chips. Background technique [0002] The packaging method and related packaging structure of power chips are relatively solid in the prior art. For example, there are representative technical contents in relevant patent documents. Chinese invention patent CN200910032590.5 discloses packaging for high-power chips Method, the core of this technology is to punch a hole slightly smaller than the copper base on the metal substrate, embed the copper base into the metal substrate, print solder paste on the copper base and the metal substrate, and install the chip and the lead pins on the copper base and the copper base respectively. On the metal substrate, put the chip, lead pin, copper base and metal substrate together in a sintering furnace for sintering at a temperature of 210°C to 230°C. The chip and the lead pin are bonded with wires, and check under...

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Problems solved by technology

[0003] In this technology, the chip is exposed on the substrate, which is actually more conducive to heat dissipation, but the packaging method or structure of this technical framework also has many disadvantages. For example, this packaging also requires a package. In fact, the package It is a safety protection cover, which can solve some safety protection problems, but this kind of enclosure may greatly reduce the effect of heat dissipation, because the enclosure is closed, so it is not conducive to heat dissipation; so now there is a lack of a technology that can retain Encapsulate this structure to ensure safety, and can also have a significant heat dissipation effect packaging technology

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