Apparatuses and methods for controlling internal reset signal and electronic system
A reset signal, external reset technology, applied in the direction of automatic power control, generation/distribution of signals, electrical components, etc., can solve the problems of different phases, changes, metastability, etc., to avoid the effect of metastability problems
Pending Publication Date: 2022-01-04
MEDIATEK INC
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Problems solved by technology
Although these dividers can output LOs of the same frequency, the phases of these LOs can be different and change, which can cause meta-stability problems
Method used
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Embodiment Construction
[0023] figure 1 An exemplary local divider reset (LORST) circuit 100 in accordance with an embodiment of the present invention is shown. The LORST circuit 100 includes a clock switch circuit 101 and a plurality (eg, M) of D flip-flops (DFFs) coupled in series.
[0024] The clock switching circuit 101 receives the clock signal CLK and is controlled by a reset signal RST. The clock signal CLK may be a global clock signal or a local clock signal. The reset signal RST may be a global reset signal or a local reset signal. In the present invention, the clock signal CLK and the reset signal RST may also be referred to as an external clock signal and an external reset signal, respectively. Note that the external reset signal RST does not have timing information of the external clock signal CLK. That is, the external reset signal RST may not be synchronized with the external clock signal CLK.
[0025] The clock switching circuit 101 includes a switch 102 and an inverter 103 . The...
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Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal; and an electronic system. The apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal. Through the apparatuses and the methods, the internal reset signal can be synchronous with the clock signal, and a metastable state problem between different transmitter paths can be avoided.
Description
technical field [0001] The present invention relates to electronic systems and, more particularly, to the field of frequency dividers that generate local oscillator signals. Background technique [0002] The background description provided herein is for the purpose of generally presenting this disclosure. Nothing described in this Background section, nor anything else described as prior art at the time of filing, should be admitted, expressly or implicitly, to be prior art to the present invention. [0003] A transceiver may have multiple transmitter (TX) paths. Each path may have its own local oscillator (LO) signal, which may be generated by a divide-by-2 (Div2) divider associated with the path. Although these dividers can output LOs of the same frequency, the phases of these LOs may be different and change, which can cause meta-stability issues. To avoid the metastability problem, the different dividers need to be synchronized so that their phase difference can be kept...
Claims
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IPC IPC(8): H03L7/18H03L7/099H03L7/08
CPCH03L7/18H03L7/0992H03L7/0807H03L7/0805G06F1/06G06F1/10G06F1/12H03K21/10H03K23/44H03K23/54H03K5/133H03K5/135H03K5/14H03K3/037
Inventor 曾乾玮穆罕默德·法提·阿布德法塔·哈桑赖力新叶姿妤蔡明达柏纳得·马克·坦博克
Owner MEDIATEK INC