Correlation judgment method and system for wafer test parameters

A technology of correlation judgment and wafer testing, which is applied in the direction of single semiconductor device testing, measuring electronics, measuring devices, etc., can solve problems such as difficulty in finding out, manpower confirmation, and difficulty in correlation, so as to improve accuracy, save time and cost effect

Pending Publication Date: 2022-01-14
SEMITRONIX
View PDF0 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the types of WAT parameters are very complicated. Through different test methods, different types of test parameters can be obtained, which may reach more than 300. It is not easy to find problems in WAT parameters manually.
On the other hand, differ

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Correlation judgment method and system for wafer test parameters
  • Correlation judgment method and system for wafer test parameters

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0022] Example one

[0023] This embodiment provides a correlation method of correlation with a wafer test parameter, which is determined for correlation to the wafer test parameter group under different test methods, such as figure 1 As shown, specific includes:

[0024] Step S1. The crystal circular electrical test is obtained using N test methods to obtain the test results, i.e., N test parameter groups.

[0025] Step S2. Data pretreatment for each test parameter group, obtains N first parameter groups, so that the parameter distribution of each first parameter group conforms to a normal distribution or a logarithmic distribution.

[0026] Step S3. Preset feature dimension g, g is positive integersion; the n first parameter groups are extracted and dropped, respectively, to obtain N second parameter groups, and the second parameter group includes g and typographic data.

[0027] Step S4. Determine the number of n second parameter groups to be packet, remember to k; and find K s...

Example Embodiment

[0030] Example 2

[0031] In this embodiment, the method of data acquisition is specifically: acquiring N test parameter groups, each test parameter group is the electrical parameters measured under a test method, and different test parameter groups are under different test methods. The measured; each electrical parameter in the test parameter group corresponds to the test result obtained by the test unit in a position coordinator in the wafer.

[0032]In this embodiment, each test parameter group includes several electrical parameters, that is, a number of measured parameter values; each electrical parameter corresponds to a grain coordinate (x, y) to cover the entire wafer. All crystal grains to be crystallized; a single unit die on a wafer (WAFER). A test parameter group is a set of parameter values ​​measured in a wafer under a test method; in other embodiments, it is also possible to take a test data after the test data of a plurality of wafers. .

[0033] In this embodiment,...

Example Embodiment

[0034] Example three

[0035] In this embodiment, the method of data pretreatment includes:

[0036] Each test parameter group is in turn: remove the group value, add a missing data, test normal distribution, and standardization.

[0037] Removing the group value means that the parameters exceeding the preset data range in the test parameter group are determined as the ionomer and delete. In this embodiment, the definition (Q 1 -1.5iQR, Q 3 The point other than + 1.5IQR is the lywood, IQR = Q 3 -Q 1 .

[0038] Add a missing data, refers to the preset number of parameter values ​​in each set of test parameters, and finds the position coordinates of the missing electrical parameters in the corresponding wafer, and uses the interpolation method to add missing data. In the present embodiment, the contrast is constructed by the discrete point, the gridized existing grain coordinate range (X 1 Y 1 ) To (x n Y n ), Use the semantian geometric correction parameter, which uses linear corre...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a correlation judgment method for wafer test parameters, which comprises the following steps of: acquiring data to obtain N test parameter groups; performing data preprocessing on the N test parameter groups to obtain N first parameter groups; carrying out dimensionality reduction on the N first parameter groups to obtain N second parameter groups; determining the number k of the N second parameter groups to be grouped to obtain k initial centroids; and automatically grouping and carrying out correlation judgment. By adopting the method, the correlation of wafer test parameters under different test methods can be automatically identified, a wafer test parameter group with high correlation can be quickly found, data analysis can be quickly performed, and time and cost are saved; and the accuracy of yield analysis can be further improved. The invention further provides a system for judging the correlation of the wafer test parameters. The system has corresponding advantages due to the adoption of the method for judging the correlation of the wafer test.

Description

technical field [0001] The invention relates to the field of semiconductor design and production, in particular to a method and system for determining the correlation of wafer test parameters measured under different test methods. Background technique [0002] With the continuous expansion of the design scale of integrated circuits, the density of electronic devices on a single chip is getting higher and higher, while the feature size of electronic devices is getting smaller and smaller. At the same time, the integrated circuit process flow contains many complicated process steps, and each step has specific process manufacturing deviations, which leads to a decrease in the yield of integrated circuit chips. In the context of design for manufacturability, in order to improve the yield of integrated circuit products and shorten the yield maturity cycle, wafer qualification testing (WAT) is usually used to perform electrical testing on wafers to obtain manufacturing processes a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G01R31/26G06K9/62
CPCG01R31/2601G06F18/2135G06F18/23213
Inventor 邵康鹏
Owner SEMITRONIX
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap