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Correlation judgment method and system for wafer test parameters

A technology of correlation judgment and wafer testing, which is applied in the direction of single semiconductor device testing, measuring electronics, measuring devices, etc., can solve problems such as difficulty in finding out, manpower confirmation, and difficulty in correlation, so as to improve accuracy, save time and cost effect

Pending Publication Date: 2022-01-14
SEMITRONIX
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the types of WAT parameters are very complicated. Through different test methods, different types of test parameters can be obtained, which may reach more than 300. It is not easy to find problems in WAT parameters manually.
On the other hand, different WAT parameters may be correlated with each other; when a certain parameter is out of the preset range, other parameters related to this parameter may also be out of the preset range, but this correlation is difficult to pass easily. Manpower Confirmation

Method used

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  • Correlation judgment method and system for wafer test parameters
  • Correlation judgment method and system for wafer test parameters

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Embodiment 1

[0023] This embodiment provides a method for determining the correlation of wafer test parameters, and performs correlation determination for wafer test parameter groups under different test methods, such as figure 1 shown, including:

[0024] Step S1. Using N kinds of test methods to conduct wafer electrical tests to obtain test results, that is, to obtain N test parameter groups.

[0025] Step S2. Perform data preprocessing on each test parameter group to obtain N first parameter groups, so that the parameter distribution of each first parameter group conforms to normal distribution or lognormal distribution.

[0026] Step S3. Preset feature dimension g, where g is a positive integer; perform feature extraction and dimensionality reduction on the N first parameter groups, respectively, to obtain N second parameter groups, and the second parameter groups include g-dimensional feature data.

[0027] Step S4. Determine the number of N second parameter groups to be grouped, den...

Embodiment 2

[0031] In this embodiment, the method for data acquisition is specifically: acquiring N test parameter groups, each test parameter group is an electrical parameter measured under a test method, and different test parameter groups are obtained under different test methods Measured; each electrical parameter in the test parameter group corresponds to a test result obtained by performing an electrical test on a test unit at a position coordinate in the wafer.

[0032]In this embodiment, each test parameter group includes several electrical parameters, that is, several measured parameter values; each electrical parameter corresponds to a grain coordinate (x, y) to cover the entire wafer. All die to be tested; a die is a single unit die on a wafer. A test parameter group is a set of parameter values ​​measured for all crystal grains in a wafer under a test method; in other embodiments, it can also be the test data after taking the median value of the test data of multiple wafers ....

Embodiment 3

[0035] In this embodiment, the method for data preprocessing specifically includes:

[0036] Separately for each test parameter group in turn: remove outliers, add missing data, test for normal distribution, and standardize.

[0037] Removing outliers refers to judging and deleting parameters in the test parameter group that exceed the preset data range as outliers. In this example, define (Q 1 -1.5IQR,Q 3 +1.5IQR) are outliers, IQR=Q 3 -Q 1 .

[0038] Adding missing data means that each set of test parameters includes a preset number of parameter values ​​to correspond to the position coordinates in the wafer one by one, find out the position coordinates of missing electrical parameters, and add missing data by interpolation. In the present embodiment, the contour line is constructed by discrete points, and the existing grain coordinate range (x 1 ,y 1 ) to (x n ,y n ), using the resampling geometry to correct the parameter values, here a linear correction is used. ...

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Abstract

The invention provides a correlation judgment method for wafer test parameters, which comprises the following steps of: acquiring data to obtain N test parameter groups; performing data preprocessing on the N test parameter groups to obtain N first parameter groups; carrying out dimensionality reduction on the N first parameter groups to obtain N second parameter groups; determining the number k of the N second parameter groups to be grouped to obtain k initial centroids; and automatically grouping and carrying out correlation judgment. By adopting the method, the correlation of wafer test parameters under different test methods can be automatically identified, a wafer test parameter group with high correlation can be quickly found, data analysis can be quickly performed, and time and cost are saved; and the accuracy of yield analysis can be further improved. The invention further provides a system for judging the correlation of the wafer test parameters. The system has corresponding advantages due to the adoption of the method for judging the correlation of the wafer test.

Description

technical field [0001] The invention relates to the field of semiconductor design and production, in particular to a method and system for determining the correlation of wafer test parameters measured under different test methods. Background technique [0002] With the continuous expansion of the design scale of integrated circuits, the density of electronic devices on a single chip is getting higher and higher, while the feature size of electronic devices is getting smaller and smaller. At the same time, the integrated circuit process flow contains many complicated process steps, and each step has specific process manufacturing deviations, which leads to a decrease in the yield of integrated circuit chips. In the context of design for manufacturability, in order to improve the yield of integrated circuit products and shorten the yield maturity cycle, wafer qualification testing (WAT) is usually used to perform electrical testing on wafers to obtain manufacturing processes a...

Claims

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Application Information

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IPC IPC(8): G01R31/26G06K9/62
CPCG01R31/2601G06F18/2135G06F18/23213
Inventor 邵康鹏
Owner SEMITRONIX
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