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Configurable crossbar switch circuit and configurable crossbar switch circuit based on configurable crossbar switch circuit

A technology of cross switch and switch, applied in the field of convolution operation, can solve the problem of repeated transmission of systolic array, and achieve the effect of reducing energy consumption and improving performance

Pending Publication Date: 2022-01-14
安徽芯纪元科技有限公司
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  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Aiming at the problem that the existing systolic array requires repeated transmission of convolution operation data, the present invention proposes a configurable crossbar circuit and a configurable crossbar circuit based on it, which can flexibly import data stored in different memories into corresponding rows of the systolic array

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  • Configurable crossbar switch circuit and configurable crossbar switch circuit based on configurable crossbar switch circuit
  • Configurable crossbar switch circuit and configurable crossbar switch circuit based on configurable crossbar switch circuit
  • Configurable crossbar switch circuit and configurable crossbar switch circuit based on configurable crossbar switch circuit

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Embodiment 1

[0026] A configurable crossbar circuit, such as figure 2 As shown, it includes the read crossbar array on the front side of the arithmetic unit array and the write crossbar array on the front side of the arithmetic unit array; the input feature map is imported into the input memory stack, and the arithmetic unit array is input through the read crossbar array, and the arithmetic unit array will calculate The output feature map of is written to the output memory stack through the write crossbar.

[0027] The read crossbar array is composed of m rows and n columns of configurable read switches, image 3 Shown is a 4-row and 8-column read crossbar switch, the number of rows m ≥ the number of input memories, the number of columns n ≥ the number of rows of arithmetic units, and only one switch of the same column read switch is closed in each cycle.

[0028] The write crossbar array is composed of p rows and q columns of configurable write switches, Figure 4 It is shown as 4 rows...

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Abstract

The invention provides a configurable crossbar switch circuit and a convolution operation circuit based on the configurable crossbar switch circuit. The configurable crossbar switch circuit comprises a read crossbar switch array on the front side of an operation unit array and a write crossbar switch array on the front side of the operation unit array. An input characteristic pattern is imported into the input memory stack and is input into the arithmetic unit array through the read crossbar switch array, the arithmetic unit array writes a calculated output characteristic pattern into the output memory stack through the write crossbar switch, and at most only one of the read switches in the same column and the write switches in the same row in each period is closed. Two-dimensional convolution operation is carried out based on the convolution operation circuit, the two-dimensional convolution operation can be completed only by importing the input feature map data into an on-chip memory once, the input feature map data does not need to be imported into the memory repeatedly, and the input feature map data does not need to be transmitted between the memories, so that the performance of two-dimensional convolution calculation is improved, and energy consumption is reduced.

Description

technical field [0001] The invention relates to the technical field of convolution operation, in particular to a configurable crossbar circuit and a configurable crossbar circuit based thereon. Background technique [0002] The convolution layer is one of the basic layers of the convolutional neural network. The convolution operation is one of the most common operations in the field of deep learning, and its calculation volume accounts for more than 90% of the calculation volume of the convolutional neural network. In recent years, with the wide application of deep learning technology in computer vision, speech processing and other fields, many hardware accelerators to improve the execution efficiency of deep learning models have been proposed. Among them, the common circuit that supports convolution operation is a systolic array. figure 1 A schematic diagram of a two-dimensional convolution operation using a systolic array to calculate a 3x3 sliding window. The systolic arr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/063
CPCG06N3/063G06N3/045
Inventor 林广栋陆俊峰顾大晔黄光红
Owner 安徽芯纪元科技有限公司